diff options
| author | Chris Wilson <[email protected]> | 2015-08-23 09:24:57 +0100 |
|---|---|---|
| committer | Chris Wilson <[email protected]> | 2015-08-24 08:57:55 +0100 |
| commit | 4e5752e2b78243a71766538f62ca0a80488047a7 (patch) | |
| tree | 544fa0a867548816c2287ee0be6f81271b14bef4 /src/mesa | |
| parent | a83c36b5c0c64c717ced76db89bab900006648aa (diff) | |
i965: Always re-emit the pipeline select during invariant state emission
On the older platforms where we don't have logical contexts preserving
state across batches, we emit the invariant state setup on every batch
using the brw_invariant_state atom. This includes the pipeline selection
which is cached with the introduction of
commit 0e0e23ef537c9add672ff322f34e129a07edc55e
Author: Jordan Justen <[email protected]>
Date: Wed Apr 22 11:43:50 2015 -0700
i965/state: Emit pipeline select when changing pipelines
However, we do not reset the cache between batches on context-less
platforms resulting in us not setting the pipeline selection and can
cause GPU hangs if a media pipelined was loaded in the meantime (e.g.
mixing mplayer/gstreamer using libva and gnome-shell). A simple solution
is to just forcibly re-emit the pipeline select along with the invariant
state and reset the cache at that point.
Reported-and-tested-by: Tomasz C. <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91254
Signed-off-by: Chris Wilson <[email protected]>
Cc: Jordan Justen <[email protected]>
Cc: Kenneth Graunke <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
Cc: "10.6 11.0" <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index e9d9467d330..27511525bff 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -878,7 +878,8 @@ brw_upload_invariant_state(struct brw_context *brw) { const bool is_965 = brw->gen == 4 && !brw->is_g4x; - brw_select_pipeline(brw, BRW_RENDER_PIPELINE); + brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE); + brw->last_pipeline = BRW_RENDER_PIPELINE; if (brw->gen < 6) { /* Disable depth offset clamping. */ |