diff options
| author | Kenneth Graunke <[email protected]> | 2013-09-17 11:54:05 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-09-19 10:52:58 -0700 |
| commit | 34b11334d417fae65ebe9cf96980aea581e24893 (patch) | |
| tree | f85f17d803469d6e20a8f3d0804cdabbf5667df6 /src/mesa | |
| parent | d2d90d66d81d5f147b03628e1913bf7f9d2a0563 (diff) | |
i965: Fix writemask != 0 assertions on Sandybridge.
This fixes myriads of regressions since commit 169f9c030c16d1247a3a7629
("i965: Add an assertion that writemask != NULL for non-ARFs.").
On Sandybridge, our control flow handling (such as brw_IF) does:
brw_set_dest(p, insn, brw_imm_w(0));
insn->bits1.branch_gen6.jump_count = 0;
This results in a IMM destination with zero for the writemask. IMM
destinations are rather bizarre, but the code has been working for ages,
so I'm loathe to change it.
Fixes glxgears on Sandybridge.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index cce87522f8b..7ed3df0e5f8 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -126,8 +126,10 @@ brw_set_dest(struct brw_compile *p, struct brw_instruction *insn, else { insn->bits1.da16.dest_subreg_nr = dest.subnr / 16; insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask; - assert(dest.dw1.bits.writemask != 0 || - dest.file == BRW_ARCHITECTURE_REGISTER_FILE); + if (dest.file == BRW_GENERAL_REGISTER_FILE || + dest.file == BRW_MESSAGE_REGISTER_FILE) { + assert(dest.dw1.bits.writemask != 0); + } /* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1: * Although Dst.HorzStride is a don't care for Align16, HW needs * this to be programmed as "01". |