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authorSamuel Iglesias Gonsalvez <siglesias@igalia.com>2014-07-23 10:51:35 +0200
committerIago Toral Quiroga <itoral@igalia.com>2014-09-19 15:01:16 +0200
commit1f77bfce7debe34366942ec441eda38747a47f74 (patch)
tree035b3af3b2e66d6ef173fb1facb7a4b5d7a7b5b0 /src/mesa
parent3ea410972a9954babdcb6a0b1d4e5bc6f1ff61d2 (diff)
i965/gen6/gs: Add an additional parameter to the FF_SYNC opcode.
We will use this parameter in later patches to provide information relevant to transform feedback that needs to be set as part of the FF_SYNC message. Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h4
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4.h3
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_generator.cpp17
-rw-r--r--src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp3
4 files changed, 19 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index e4868d1c292..b2216fe9559 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1028,6 +1028,10 @@ enum opcode {
*
* - src0 is the number of primitives written.
*
+ * - src1 is the value to hold in M0.0: number of SO vertices to write
+ * and number of SO primitives needed. Its value will be overwritten
+ * with the SVBI values if transform feedback is enabled.
+ *
* Note: This opcode uses an implicit MRF register for the ff_sync message
* header, so the caller is expected to set inst->base_mrf and initialize
* that MRF register to r0. This opcode will also write to this MRF register
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index d3d374d14c2..1909cbd75d6 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -675,7 +675,8 @@ private:
struct brw_reg src2);
void generate_gs_ff_sync(vec4_instruction *inst,
struct brw_reg dst,
- struct brw_reg src0);
+ struct brw_reg src0,
+ struct brw_reg src1);
void generate_gs_set_primitive_id(struct brw_reg dst);
void generate_oword_dual_block_offsets(struct brw_reg m1,
struct brw_reg index);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index d1aeeadd102..88695381045 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -756,7 +756,8 @@ vec4_generator::generate_gs_ff_sync_set_primitives(struct brw_reg dst,
void
vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
struct brw_reg dst,
- struct brw_reg src0)
+ struct brw_reg src0,
+ struct brw_reg src1)
{
/* This opcode uses an implied MRF register for:
* - the header of the ff_sync message. And as such it is expected to be
@@ -766,14 +767,13 @@ vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
struct brw_reg header =
retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
- /* Overwrite dword 0 of the header (cleared for now since we are not doing
- * transform feedback) and dword 1 (to hold the number of primitives
- * written).
+ /* Overwrite dword 0 of the header (SO vertices to write) and
+ * dword 1 (number of primitives written).
*/
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_access_mode(p, BRW_ALIGN_1);
- brw_MOV(p, get_element_ud(header, 0), brw_imm_ud(0));
+ brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
brw_pop_insn_state(p);
@@ -791,6 +791,11 @@ vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
+
+ /* src1 is not an immediate when we use transform feedback */
+ if (src1.file != BRW_IMMEDIATE_VALUE)
+ brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
+
brw_pop_insn_state(p);
}
@@ -1441,7 +1446,7 @@ vec4_generator::generate_code(const cfg_t *cfg)
break;
case GS_OPCODE_FF_SYNC:
- generate_gs_ff_sync(inst, dst, src[0]);
+ generate_gs_ff_sync(inst, dst, src[0], src[1]);
break;
case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp b/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp
index 0da95e56011..7a832cac39b 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp
@@ -331,7 +331,8 @@ gen6_gs_visitor::emit_thread_end()
{
this->current_annotation = "gen6 thread end: ff_sync";
vec4_instruction *inst =
- emit(GS_OPCODE_FF_SYNC, dst_reg(this->temp), this->prim_count);
+ emit(GS_OPCODE_FF_SYNC, dst_reg(this->temp), this->prim_count,
+ brw_imm_ud(0u));
inst->base_mrf = base_mrf;
/* Loop over all buffered vertices and emit URB write messages */