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authorBrian Paul <[email protected]>2009-04-16 15:43:32 -0600
committerBrian Paul <[email protected]>2009-04-17 16:10:26 -0600
commitf8f23e33c21f41756d068b546f2aae37030b5773 (patch)
treeee5977886671c7d32418e7764414aff1ffdeb1e8 /src/mesa
parent867afa4c093cb05bedf11a1c7a74feb202fb858b (diff)
i965: updated CURBE allocation code
Now that we have real constant buffers, the demands on the CURBE are lessened. When we use real VS/WM constant buffers we only use the CURBE for clip planes.
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h3
-rw-r--r--src/mesa/drivers/dri/i965/brw_curbe.c14
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs_emit.c6
3 files changed, 15 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 4c2d3af8ae9..a0b3b06309f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -187,7 +187,7 @@ struct brw_wm_prog_data {
GLuint total_grf;
GLuint total_scratch;
- GLuint nr_params;
+ GLuint nr_params; /**< number of float params/constants */
GLboolean error;
/* Pointer to tracked values (only valid once
@@ -226,6 +226,7 @@ struct brw_vs_prog_data {
GLuint urb_read_length;
GLuint total_grf;
GLuint outputs_written;
+ GLuint nr_params; /**< number of float params/constants */
GLuint inputs_read;
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index fe1de821f05..18b187ed1dc 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -45,17 +45,21 @@
#include "brw_util.h"
-/* Partition the CURBE between the various users of constant values:
+/**
+ * Partition the CURBE between the various users of constant values:
+ * Note that vertex and fragment shaders can now fetch constants out
+ * of constant buffers. We no longer allocatea block of the GRF for
+ * constants. That greatly reduces the demand for space in the CURBE.
+ * Some of the comments within are dated...
*/
static void calculate_curbe_offsets( struct brw_context *brw )
{
GLcontext *ctx = &brw->intel.ctx;
/* CACHE_NEW_WM_PROG */
- GLuint nr_fp_regs = (brw->wm.prog_data->nr_params + 15) / 16;
+ const GLuint nr_fp_regs = (brw->wm.prog_data->nr_params + 15) / 16;
/* BRW_NEW_VERTEX_PROGRAM */
- const struct brw_vertex_program *vp = brw_vertex_program_const(brw->vertex_program);
- GLuint nr_vp_regs = (vp->program.Base.Parameters->NumParameters * 4 + 15) / 16;
+ const GLuint nr_vp_regs = (brw->vs.prog_data->nr_params + 15) / 16;
GLuint nr_clip_regs = 0;
GLuint total_regs;
@@ -248,7 +252,7 @@ static void prepare_constant_buffer(struct brw_context *brw)
/* vertex shader constants */
if (brw->curbe.vs_size) {
GLuint offset = brw->curbe.vs_start * 16;
- GLuint nr = vp->program.Base.Parameters->NumParameters;
+ GLuint nr = brw->vs.prog_data->nr_params / 4;
_mesa_load_state_parameters(ctx, vp->program.Base.Parameters);
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index af0f5016212..0c86c23ad91 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -68,7 +68,6 @@ static void release_tmps( struct brw_vs_compile *c )
static void brw_vs_alloc_regs( struct brw_vs_compile *c )
{
GLuint i, reg = 0, mrf;
- GLuint nr_params;
#if 0
if (c->vp->program.Base.Parameters->NumParameters >= 6)
@@ -100,15 +99,18 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
if (c->use_const_buffer) {
/* get constants from a real constant buffer */
c->prog_data.curb_read_length = 0;
+ c->prog_data.nr_params = 4; /* XXX 0 causes a bug elsewhere... */
}
else {
/* use a section of the GRF for constants */
- nr_params = c->vp->program.Base.Parameters->NumParameters;
+ GLuint nr_params = c->vp->program.Base.Parameters->NumParameters;
for (i = 0; i < nr_params; i++) {
c->regs[PROGRAM_STATE_VAR][i] = stride( brw_vec4_grf(reg+i/2, (i%2) * 4), 0, 4, 1);
}
reg += (nr_params + 1) / 2;
c->prog_data.curb_read_length = reg - 1;
+
+ c->prog_data.nr_params = nr_params * 4;
}
/* Allocate input regs: