diff options
| author | Iago Toral Quiroga <[email protected]> | 2016-09-06 08:56:05 +0200 |
|---|---|---|
| committer | Samuel Iglesias Gonsálvez <[email protected]> | 2017-01-03 11:26:51 +0100 |
| commit | 3cd38b68987f28536abd218fd62de5dc38c14aa1 (patch) | |
| tree | 1a5181e2698963d4578d3df6270a55a0ab48f661 /src/mesa | |
| parent | 8843c43f7e85423b559383b38c77477139b4b06e (diff) | |
i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destination
FROM_DOUBLE opcodes are setup so that they use a dst register
with a size of 2 even if they only produce a single-precison
result (this is so that the opcode can use the larger register to
produce a 64-bit aligned intermediary result as required by the
hardware during the conversion process). This creates a problem for
spilling though, because when we attempt to emit a spill for the
dst we see a 32-bit destination and emit a scratch write that
allocates a single spill register, making the intermediary writes
go beyond the size of the allocation.
Prevent this by avoiding to spill the destination register of these
opcodes.
Alternatively, we can avoid this by splitting the opcode in two: one
that produces a 64-bit aligned result and one that takes the 64-bit
aligned result as input and produces a 32-bit result from it.
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp index 79fd15b12bb..2e5bc79b485 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp @@ -436,6 +436,18 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill) if (type_sz(inst->dst.type) == 8 && inst->exec_size != 8) no_spill[inst->dst.nr] = true; + /* FROM_DOUBLE opcodes are setup so that they use a dst register + * with a size of 2 even if they only produce a single-precison + * result (this is so that the opcode can use the larger register to + * produce a 64-bit aligned intermediary result as required by the + * hardware during the conversion process). This creates a problem for + * spilling though, because when we attempt to emit a spill for the + * dst we see a 32-bit destination and emit a scratch write that + * allocates a single spill register. + */ + if (inst->opcode == VEC4_OPCODE_FROM_DOUBLE) + no_spill[inst->dst.nr] = true; + /* We can't spill registers that mix 32-bit and 64-bit access (that * contain 64-bit data that is operated on via 32-bit instructions) */ |