diff options
| author | Kenneth Graunke <[email protected]> | 2011-08-18 02:15:56 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2011-08-20 00:17:55 -0700 |
| commit | f7d2dcae3b6bf39b14c1e71f0721d0e4a2833962 (patch) | |
| tree | 9edea00102cdcab8940b9bad7b44d752d4c0cceb /src/mesa | |
| parent | e98ee06776e0ba055e0194836d5813a0bc7e7795 (diff) | |
i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables.
Makes the new vertex shader backend work on Ivybridge.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 27e81306e9c..c5013de7ec1 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -2244,10 +2244,13 @@ void brw_urb_WRITE(struct brw_compile *p, if (intel->gen == 7) { /* Enable Channel Masks in the URB_WRITE_HWORD message header */ + brw_push_insn_state(p); + brw_set_access_mode(p, BRW_ALIGN_1); brw_OR(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 5), BRW_REGISTER_TYPE_UD), retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), brw_imm_ud(0xff00)); + brw_pop_insn_state(p); } insn = next_insn(p, BRW_OPCODE_SEND); |