diff options
| author | Kenneth Graunke <[email protected]> | 2014-10-22 08:58:59 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-11-04 11:39:18 -0800 |
| commit | 6107557f8fa34e0b7191813792be43eaa03aed19 (patch) | |
| tree | 270bf1d08c302860ed27066d71806e6ce1c94adc /src/mesa | |
| parent | 7423cc891b4d6fcc63bfeb79cc1d711ce81122bd (diff) | |
i965: Re-enable Z16 on Gen8+.
Improves performance in GLBenchmark 2.7 TRex by 3.88889% +/- 0.336383%
(n=80) at 1280x720 on Broadwell GT3. Together with the previous patch,
it improves performance by 5.42738% +/- 0.541971% (n=10) at 1920x1080.
Note that without the PMA stall fix, this would instead decrease
performance by 22%.
v2: Update comment (noticed by Kristian Høgsberg).
Signed-off-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_surface_formats.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c index 5407ef65576..2841f819f43 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c @@ -619,6 +619,8 @@ brw_init_surface_formats(struct brw_context *brw) brw->format_supported_as_render_target[MESA_FORMAT_S_UINT8] = true; brw->format_supported_as_render_target[MESA_FORMAT_Z_FLOAT32] = true; brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true; + if (brw->gen >= 8) + brw->format_supported_as_render_target[MESA_FORMAT_Z_UNORM16] = true; /* We remap depth formats to a supported texturing format in * translate_tex_format(). @@ -638,7 +640,12 @@ brw_init_surface_formats(struct brw_context *brw) * * Other speculation is that we may be hitting increased fragment shader * execution from GL_LEQUAL/GL_EQUAL depth tests at reduced precision. + * + * With the PMA stall workaround in place, Z16 is faster than Z24, as it + * should be. */ + if (brw->gen >= 8) + ctx->TextureFormatSupported[MESA_FORMAT_Z_UNORM16] = true; /* On hardware that lacks support for ETC1, we map ETC1 to RGBX * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1. |