diff options
author | Eugeni Dodonov <[email protected]> | 2012-03-31 12:38:59 -0300 |
---|---|---|
committer | Eugeni Dodonov <[email protected]> | 2012-04-01 10:50:55 -0300 |
commit | a45247fb1b8c30c5be21c3baf84943920ae17bfb (patch) | |
tree | 979d7c5b7ef5f26c660d9ba4ac11f64127fbc5b9 /src/mesa | |
parent | 4123d0b32138a0fbdbc7f61380d041704ba0ad43 (diff) |
intel: add PCI IDs for Ivy Bridge GT2 server variant
Those IDs are used by Bromolow.
Reviewed-by: Kenneth Graunke <[email protected]>
Signed-off-by: Eugeni Dodonov <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_chipset.h | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.c | 1 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 424c70ce2f1..c1d904ee998 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -85,6 +85,7 @@ #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */ #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */ +#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ #define PCI_CHIP_HASWELL_GT2 0x0412 @@ -153,7 +154,8 @@ devid == PCI_CHIP_IVYBRIDGE_S_GT1) #define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \ - devid == PCI_CHIP_IVYBRIDGE_M_GT2) + devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \ + devid == PCI_CHIP_IVYBRIDGE_S_GT2) #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || IS_IVB_GT2(devid)) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index ff2b7feec8d..0a813a46b4f 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -183,6 +183,7 @@ intelGetString(struct gl_context * ctx, GLenum name) chipset = "Intel(R) Ivybridge Mobile"; break; case PCI_CHIP_IVYBRIDGE_S_GT1: + case PCI_CHIP_IVYBRIDGE_S_GT2: chipset = "Intel(R) Ivybridge Server"; break; case PCI_CHIP_HASWELL_GT1: |