diff options
| author | Eric Anholt <[email protected]> | 2012-05-21 09:13:33 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2012-05-23 10:18:26 -0700 |
| commit | 03c9044c2edf8301779fe5d0173d7e6d1e7ee1c2 (patch) | |
| tree | b09a7bcf9d4b2763cb4ae0653ef6717eb14b8937 /src/mesa | |
| parent | 11892ea986b5fdad345ce7c09f97e0389e546509 (diff) | |
i915: Drop gen4+ code from the forked clear code.
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_clear.c | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i915/intel_clear.c b/src/mesa/drivers/dri/i915/intel_clear.c index 331635148f6..96d9c8fe682 100644 --- a/src/mesa/drivers/dri/i915/intel_clear.c +++ b/src/mesa/drivers/dri/i915/intel_clear.c @@ -89,9 +89,6 @@ intelClear(struct gl_context *ctx, GLbitfield mask) struct intel_renderbuffer *irb; int i; - if (!_mesa_check_conditional_render(ctx)) - return; - if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) { intel->front_buffer_dirty = true; } @@ -116,7 +113,7 @@ intelClear(struct gl_context *ctx, GLbitfield mask) } /* HW color buffers (front, back, aux, generic FBO, etc) */ - if (intel->gen < 6 && colorMask == ~0) { + if (colorMask == ~0) { /* clear all R,G,B,A */ blit_mask |= (mask & BUFFER_BITS_COLOR); } @@ -143,12 +140,6 @@ intelClear(struct gl_context *ctx, GLbitfield mask) */ tri_mask |= BUFFER_BIT_STENCIL; } - else if (intel->has_separate_stencil && - stencilRegion->tiling == I915_TILING_NONE) { - /* The stencil buffer is actually W tiled, which the hardware - * cannot blit to. */ - tri_mask |= BUFFER_BIT_STENCIL; - } else { /* clearing all stencil bits, use blitting */ blit_mask |= BUFFER_BIT_STENCIL; |