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authorEric Anholt <[email protected]>2014-03-04 15:12:40 -0800
committerEric Anholt <[email protected]>2014-03-05 13:37:33 -0800
commit171ec9585f214c2dff3cfc97acebf5286bb5001d (patch)
treefc01dd218467da96f8ae6da35ea6cf84f5e6c4b5 /src/mesa
parent9856d658ced3382060f4d805f3e4fbdc2b618e64 (diff)
i965: Fix predicated-send-based discards with MRT.
We need the header setup to not be predicated on which pixels are undiscarded. I'm not sure originally if I had thought that the mask disable implied predicate disable, or if I had just misread the mask disable as predicate disable. Either way, I know I had spent more time thinking about this in the gen8 generator than the gen7 generator. Plus, it turns out that I had mis-implemented the "the GPU will use the predicate unless this header is present" comment, by skipping setting up the pixel mask when the header was present. Fixes GPU hangs in piglit glsl-fs-discard-mrt, Trine, Trine 2 and preusmably MLL. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75207 Tested-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_generator.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 748a2e2db12..e590bdf4c58 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -103,14 +103,14 @@ fs_generator::generate_fb_write(fs_inst *inst)
*/
brw_push_insn_state(p);
brw_set_mask_control(p, BRW_MASK_DISABLE);
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
if (inst->header_present) {
/* On HSW, the GPU will use the predicate on SENDC, unless the header is
* present.
*/
- if (!brw->is_haswell && ((fp && fp->UsesKill) ||
- c->key.alpha_test_func)) {
+ if ((fp && fp->UsesKill) || c->key.alpha_test_func) {
struct brw_reg pixel_mask;
if (brw->gen >= 6)