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authorMichel Dänzer <[email protected]>2007-02-28 16:05:49 +0100
committerMichel Dänzer <[email protected]>2007-02-28 16:05:49 +0100
commitedf676cc5af26d8f82625a94788d4f27c464ab38 (patch)
tree3ef7cbc0b7941c72db6458453cf8183bc78279c8 /src/mesa
parent641c966e3de192eba17c693f00d6654742c72eb6 (diff)
i915tex: Also update intel_rb->vbl_pending when scheduled swap is not a flip.
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i915tex/intel_buffers.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i915tex/intel_buffers.c b/src/mesa/drivers/dri/i915tex/intel_buffers.c
index 8054d98646b..5eb2a8e5d09 100644
--- a/src/mesa/drivers/dri/i915tex/intel_buffers.c
+++ b/src/mesa/drivers/dri/i915tex/intel_buffers.c
@@ -815,12 +815,12 @@ intelScheduleSwap(const __DRIdrawablePrivate * dPriv, GLboolean *missed_target)
swap.sequence -= target;
*missed_target = swap.sequence > 0 && swap.sequence <= (1 << 23);
- if (swap.seqtype & DRM_VBLANK_FLIP) {
+ intel_get_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT)->vbl_pending =
intel_get_renderbuffer(&intel_fb->Base,
BUFFER_FRONT_LEFT)->vbl_pending =
- intel_get_renderbuffer(&intel_fb->Base,
- BUFFER_BACK_LEFT)->vbl_pending = intel_fb->vbl_seq;
+ intel_fb->vbl_seq;
+ if (swap.seqtype & DRM_VBLANK_FLIP) {
intel_flip_renderbuffers(intel_fb);
intel_draw_buffer(&intel->ctx, intel->ctx.DrawBuffer);
}