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authorEric Anholt <[email protected]>2011-04-22 13:25:24 -0700
committerEric Anholt <[email protected]>2011-04-29 15:25:45 -0700
commit8d2047ca7e8a533e1853a2ba51cd1bd6e52ae4a3 (patch)
tree65624afbadf8fb95f8edfd37b8f3a13adf6ab63b /src/mesa
parent3628e123f13a480abfad8e8af9f875e3d8eeb5a6 (diff)
i965/gen6: Move the SF VP to state streaming.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_sf_state.c7
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_dump.c12
-rw-r--r--src/mesa/drivers/dri/i965/brw_vtbl.c1
-rw-r--r--src/mesa/drivers/dri/i965/gen6_viewport_state.c29
5 files changed, 20 insertions, 30 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index b6cd058d5c2..70a03f6f915 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -672,7 +672,6 @@ struct brw_context
drm_intel_bo *prog_bo;
drm_intel_bo *state_bo;
uint32_t state_offset;
- drm_intel_bo *vp_bo;
uint32_t vp_offset;
} sf;
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 66d91a0bde7..0fa1dc90dcd 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -106,11 +106,6 @@ static void upload_sf_vp(struct brw_context *brw)
sfv->scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
}
- /* Keep a pointer to it for brw_state_dump.c */
- drm_intel_bo_unreference(brw->sf.vp_bo);
- drm_intel_bo_reference(intel->batch.bo);
- brw->sf.vp_bo = intel->batch.bo;
-
brw->state.dirty.cache |= CACHE_NEW_SF_VP;
}
@@ -177,7 +172,7 @@ static void upload_sf_unit( struct brw_context *brw )
sf->thread4.stats_enable = 1;
/* CACHE_NEW_SF_VP */
- sf->sf5.sf_viewport_state_offset = (brw->sf.vp_bo->offset +
+ sf->sf5.sf_viewport_state_offset = (intel->batch.bo->offset +
brw->sf.vp_offset) >> 5; /* reloc */
sf->sf5.viewport_transform = 1;
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c
index 03e03e30e79..2d030c27096 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -204,17 +204,15 @@ static void dump_wm_sampler_state(struct brw_context *brw)
static void dump_sf_viewport_state(struct brw_context *brw)
{
+ struct intel_context *intel = &brw->intel;
const char *name = "SF VP";
struct brw_sf_viewport *vp;
uint32_t vp_off;
- if (brw->sf.vp_bo == NULL)
- return;
-
- drm_intel_bo_map(brw->sf.vp_bo, GL_FALSE);
+ drm_intel_bo_map(intel->batch.bo, GL_FALSE);
- vp = brw->sf.vp_bo->virtual + brw->sf.vp_offset;
- vp_off = brw->sf.vp_bo->offset + brw->sf.vp_offset;
+ vp = intel->batch.bo->virtual + brw->sf.vp_offset;
+ vp_off = intel->batch.bo->offset + brw->sf.vp_offset;
state_out(name, vp, vp_off, 0, "m00 = %f\n", vp->viewport.m00);
state_out(name, vp, vp_off, 1, "m11 = %f\n", vp->viewport.m11);
@@ -228,7 +226,7 @@ static void dump_sf_viewport_state(struct brw_context *brw)
state_out(name, vp, vp_off, 7, "bottom right = %d,%d\n",
vp->scissor.xmax, vp->scissor.ymax);
- drm_intel_bo_unmap(brw->sf.vp_bo);
+ drm_intel_bo_unmap(intel->batch.bo);
}
static void dump_clip_viewport_state(struct brw_context *brw)
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index b4d5a99c173..5b8338b78e5 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -85,7 +85,6 @@ static void brw_destroy_context( struct intel_context *intel )
dri_bo_release(&brw->clip.state_bo);
dri_bo_release(&brw->sf.prog_bo);
dri_bo_release(&brw->sf.state_bo);
- dri_bo_release(&brw->sf.vp_bo);
for (i = 0; i < BRW_MAX_TEX_UNIT; i++)
dri_bo_release(&brw->wm.sdc_bo[i]);
dri_bo_release(&brw->wm.sampler_bo);
diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
index 6512123201b..32fdd953c4d 100644
--- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
@@ -67,12 +67,13 @@ prepare_sf_vp(struct brw_context *brw)
{
struct gl_context *ctx = &brw->intel.ctx;
const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
- struct brw_sf_viewport sfv;
+ struct brw_sf_viewport *sfv;
GLfloat y_scale, y_bias;
const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
const GLfloat *v = ctx->Viewport._WindowMap.m;
- memset(&sfv, 0, sizeof(sfv));
+ sfv = brw_state_batch(brw, sizeof(*sfv), 32, &brw->sf.vp_offset);
+ memset(sfv, 0, sizeof(*sfv));
/* _NEW_BUFFERS */
if (render_to_fbo) {
@@ -84,22 +85,20 @@ prepare_sf_vp(struct brw_context *brw)
}
/* _NEW_VIEWPORT */
- sfv.viewport.m00 = v[MAT_SX];
- sfv.viewport.m11 = v[MAT_SY] * y_scale;
- sfv.viewport.m22 = v[MAT_SZ] * depth_scale;
- sfv.viewport.m30 = v[MAT_TX];
- sfv.viewport.m31 = v[MAT_TY] * y_scale + y_bias;
- sfv.viewport.m32 = v[MAT_TZ] * depth_scale;
-
- drm_intel_bo_unreference(brw->sf.vp_bo);
- brw->sf.vp_bo = brw_cache_data(&brw->cache, BRW_SF_VP,
- &sfv, sizeof(sfv));
+ sfv->viewport.m00 = v[MAT_SX];
+ sfv->viewport.m11 = v[MAT_SY] * y_scale;
+ sfv->viewport.m22 = v[MAT_SZ] * depth_scale;
+ sfv->viewport.m30 = v[MAT_TX];
+ sfv->viewport.m31 = v[MAT_TY] * y_scale + y_bias;
+ sfv->viewport.m32 = v[MAT_TZ] * depth_scale;
+
+ brw->state.dirty.cache |= CACHE_NEW_SF_VP;
}
const struct brw_tracked_state gen6_sf_vp = {
.dirty = {
.mesa = _NEW_VIEWPORT | _NEW_BUFFERS,
- .brw = 0,
+ .brw = BRW_NEW_BATCH,
.cache = 0,
},
.prepare = prepare_sf_vp,
@@ -107,7 +106,6 @@ const struct brw_tracked_state gen6_sf_vp = {
static void prepare_viewport_state_pointers(struct brw_context *brw)
{
- brw_add_validated_bo(brw, brw->sf.vp_bo);
brw_add_validated_bo(brw, brw->cc.vp_bo);
}
@@ -122,7 +120,8 @@ static void upload_viewport_state_pointers(struct brw_context *brw)
GEN6_CLIP_VIEWPORT_MODIFY);
OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
brw->clip.vp_offset);
- OUT_RELOC(brw->sf.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ brw->sf.vp_offset);
OUT_RELOC(brw->cc.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
ADVANCE_BATCH();
}