diff options
| author | Paul Berry <[email protected]> | 2013-03-23 08:23:03 -0700 |
|---|---|---|
| committer | Paul Berry <[email protected]> | 2013-03-24 10:55:27 -0700 |
| commit | 76ba30800d08149386c0bc6a6c5efc50590d3048 (patch) | |
| tree | b34fe11c3ff4507045e9059aa1ced5d0e953c555 /src/mesa | |
| parent | 8371c68a4b4c12f4dd75f82b8b29a624705910a5 (diff) | |
i965/gen7: Use WE_all mode when enabling channel masks for URB write.
Gen7 adds mask bits to the message header for a URB write which allow
the write to apply only to certain channels. We don't use this
functionality, so to ensure that the entire write always occurs, we
emit an OR instruction to set the mask bits.
With the advent of geometry shaders, URB writes won't just happen at
the end of a thread; they will happen in mid-thread too. Thus, we can
no longer rely on channel 0 being enabled, so we need to emit the OR
instruction in WE_all mode to ensure that it is executed.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 992e784225b..23556264269 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -2184,6 +2184,7 @@ void brw_urb_WRITE(struct brw_compile *p, /* Enable Channel Masks in the URB_WRITE_HWORD message header */ brw_push_insn_state(p); brw_set_access_mode(p, BRW_ALIGN_1); + brw_set_mask_control(p, BRW_MASK_DISABLE); brw_OR(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 5), BRW_REGISTER_TYPE_UD), retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), |