r300g: fix RG/LATC1_SNORM by doing UNORM->SNORM conversion in the shader

2 files changed, 60 insertions, 6 deletions

diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_code.h b/src/mesa/drivers/dri/r300/compiler/radeon_code.h
index 35360aa70f0..67e6acf8b10 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_code.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_code.h
@@ -132,10 +132,10 @@ typedef enum {
 struct r300_fragment_program_external_state {
 	struct {
 		/**
-		 * If the sampler is used as a shadow sampler,
-		 * this field contains swizzle depending on the depth texture mode.
+		 * This field contains swizzle for some lowering passes
+		 * (shadow comparison, unorm->snorm conversion)
 		 */
-		unsigned depth_texture_swizzle:12;
+		unsigned texture_swizzle:12;
 
 		/**
 		 * If the sampler is used as a shadow sampler,
@@ -172,6 +172,12 @@ struct r300_fragment_program_external_state {
 		 * and right before texture fetch. The scaling factor is given by
 		 * RC_STATE_R300_TEXSCALE_FACTOR. */
 		unsigned clamp_and_scale_before_fetch : 1;
+
+		/**
+		 * Fetch RGTC1_SNORM or LATC1_SNORM as UNORM and convert UNORM -> SNORM
+		 * in the shader.
+		 */
+		unsigned convert_unorm_to_snorm:1;
 	} unit[16];
 
 	unsigned frag_clamp:1;
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
index 97225808d4d..cef448ee4e1 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
@@ -48,7 +48,7 @@ static struct rc_src_register shadow_fail_value(struct r300_fragment_program_com
 	}
 
 	reg.Swizzle = combine_swizzles(reg.Swizzle,
-				compiler->state.unit[tmu].depth_texture_swizzle);
+				compiler->state.unit[tmu].texture_swizzle);
 	return reg;
 }
 
@@ -59,7 +59,7 @@ static struct rc_src_register shadow_pass_value(struct r300_fragment_program_com
 
 	reg.File = RC_FILE_NONE;
 	reg.Swizzle = combine_swizzles(RC_SWIZZLE_1111,
-				compiler->state.unit[tmu].depth_texture_swizzle);
+				compiler->state.unit[tmu].texture_swizzle);
 	return reg;
 }
 
@@ -256,7 +256,7 @@ int radeonTransformTEX(
 			inst_cmp->U.I.SrcReg[0].Index = tmp_sum;
 			inst_cmp->U.I.SrcReg[0].Swizzle =
 					combine_swizzles(RC_SWIZZLE_WWWW,
-							 compiler->state.unit[inst->U.I.TexSrcUnit].depth_texture_swizzle);
+							 compiler->state.unit[inst->U.I.TexSrcUnit].texture_swizzle);
 			inst_cmp->U.I.SrcReg[pass] = shadow_pass_value(compiler, inst->U.I.TexSrcUnit);
 			inst_cmp->U.I.SrcReg[fail] = shadow_fail_value(compiler, inst->U.I.TexSrcUnit);
 
@@ -411,6 +411,7 @@ int radeonTransformTEX(
 		inst->U.I.SrcReg[0].Index = temp;
 	}
 
+	/* NPOT -> POT conversion for 3D textures. */
 	if (inst->U.I.Opcode != RC_OPCODE_KIL &&
 	    compiler->state.unit[inst->U.I.TexSrcUnit].clamp_and_scale_before_fetch) {
 		struct rc_instruction *inst_mov;
@@ -440,6 +441,53 @@ int radeonTransformTEX(
 		scale_texcoords(compiler, inst, RC_STATE_R300_TEXSCALE_FACTOR);
 	}
 
+	/* Convert SNORM-encoded ATI1N sampled as UNORM to SNORM.
+	 * Formula: dst = tex > 0.5 ? tex*2-2 : tex*2
+	 */
+	if (inst->U.I.Opcode != RC_OPCODE_KIL &&
+	    compiler->state.unit[inst->U.I.TexSrcUnit].convert_unorm_to_snorm) {
+		unsigned two, two_swizzle;
+		struct rc_instruction *inst_mul, *inst_mad, *inst_cnd;
+
+		two = rc_constants_add_immediate_scalar(&c->Program.Constants, 2.35, &two_swizzle);
+
+		inst_mul = rc_insert_new_instruction(c, inst);
+		inst_mul->U.I.Opcode = RC_OPCODE_MUL;
+		inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY;
+		inst_mul->U.I.DstReg.Index = rc_find_free_temporary(c);
+		inst_mul->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
+		inst_mul->U.I.SrcReg[0].Index = rc_find_free_temporary(c); /* redirected TEX output */
+		inst_mul->U.I.SrcReg[1].File = RC_FILE_CONSTANT; /* 2 */
+		inst_mul->U.I.SrcReg[1].Index = two;
+		inst_mul->U.I.SrcReg[1].Swizzle = two_swizzle;
+
+		inst_mad = rc_insert_new_instruction(c, inst_mul);
+		inst_mad->U.I.Opcode = RC_OPCODE_MAD;
+		inst_mad->U.I.DstReg.File = RC_FILE_TEMPORARY;
+		inst_mad->U.I.DstReg.Index = rc_find_free_temporary(c);
+		inst_mad->U.I.SrcReg[0] = inst_mul->U.I.SrcReg[0]; /* redirected TEX output */
+		inst_mad->U.I.SrcReg[1] = inst_mul->U.I.SrcReg[1]; /* 2 */
+		inst_mad->U.I.SrcReg[2] = inst_mul->U.I.SrcReg[1]; /* 2 */
+		inst_mad->U.I.SrcReg[2].Negate = RC_MASK_XYZW;
+
+		inst_cnd = rc_insert_new_instruction(c, inst_mad);
+		inst_cnd->U.I.Opcode = RC_OPCODE_CND;
+		inst_cnd->U.I.SaturateMode = inst->U.I.SaturateMode;
+		inst_cnd->U.I.DstReg = inst->U.I.DstReg;
+		inst_cnd->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
+		inst_cnd->U.I.SrcReg[0].Index = inst_mad->U.I.DstReg.Index;
+		inst_cnd->U.I.SrcReg[0].Swizzle = compiler->state.unit[inst->U.I.TexSrcUnit].texture_swizzle;
+		inst_cnd->U.I.SrcReg[1].File = RC_FILE_TEMPORARY;
+		inst_cnd->U.I.SrcReg[1].Index = inst_mul->U.I.DstReg.Index;
+		inst_cnd->U.I.SrcReg[1].Swizzle = compiler->state.unit[inst->U.I.TexSrcUnit].texture_swizzle;
+		inst_cnd->U.I.SrcReg[2] = inst_mul->U.I.SrcReg[0]; /* redirected TEX output */
+
+		inst->U.I.SaturateMode = 0;
+		inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
+		inst->U.I.DstReg.Index = inst_mul->U.I.SrcReg[0].Index;
+		inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
+	}
+
 	/* Cannot write texture to output registers or with saturate (all chips),
 	 * or with masks (non-r500). */
 	if (inst->U.I.Opcode != RC_OPCODE_KIL &&