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authorKenneth Graunke <[email protected]>2011-09-26 23:57:40 -0700
committerKenneth Graunke <[email protected]>2011-09-28 00:52:43 -0700
commit83df7fbe62be2798d557142a47e01af86ec9e2e2 (patch)
tree97b76bc58822a8be8a1337ed09a49d030d49619e /src/mesa
parent79cba4c2b17456e2b25ac555c45e1c106b4e3f6b (diff)
i965: Allow SIMD16 color writes on Ivybridge.
Again, the check was needlessly specific: this works fine on Gen7. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_visitor.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 60d79ef056c..e4746db6018 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1803,7 +1803,7 @@ fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color)
int reg_width = c->dispatch_width / 8;
fs_inst *inst;
- if (c->dispatch_width == 8 || intel->gen == 6) {
+ if (c->dispatch_width == 8 || intel->gen >= 6) {
/* SIMD8 write looks like:
* m + 0: r0
* m + 1: r1