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authorFrancisco Jerez <[email protected]>2015-08-05 16:43:37 +0300
committerFrancisco Jerez <[email protected]>2015-08-06 14:12:12 +0300
commitf5b37fb1acad9cf044b7b6d4fa5f2582bd8bc7f4 (patch)
tree41d69158b56da26d2e1d1ef73a2af390a9d779ca /src/mesa
parent8f5d0988ea2ccaba7f049f113b652f331524d2a6 (diff)
i965/fs: Lower 32x32 bit multiplication on BXT.
AFAIK BXT has the same annoying alignment limitation as CHV on the source register regions of 32x32 bit MULs, give it the same treatment. Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 15fe3648af8..0278237101e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3130,9 +3130,9 @@ fs_visitor::lower_integer_multiplication()
bool progress = false;
/* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit operation
- * directly, but Cherryview cannot.
+ * directly, but CHV/BXT cannot.
*/
- if (devinfo->gen >= 8 && !devinfo->is_cherryview)
+ if (devinfo->gen >= 8 && !devinfo->is_cherryview && !devinfo->is_broxton)
return false;
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {