diff options
| author | Kristian Høgsberg <[email protected]> | 2014-07-07 16:27:31 -0700 |
|---|---|---|
| committer | Kristian Høgsberg <[email protected]> | 2014-08-15 10:33:41 -0700 |
| commit | cf89b29d2f87be8ca437049e5cf3df9f54a806b2 (patch) | |
| tree | 663193c7a704f14713820c48150e93a86f383f6e /src/mesa | |
| parent | 1a05dcb349514ba3287cdfec89db9ddf951aaae8 (diff) | |
i965: Provide a context flag to let us enable fast clear
GEN7+ has the fast clear functionality, which lets us clear the color
buffers using the MCS and a scaled down rectangle. To enable this
we have to set the appropriate bits in the 3DSTATE_PS package.
Signed-off-by: Kristian Høgsberg <[email protected]>
Acked-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_ps_state.c | 2 |
3 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 01be5fb427f..19331827ce5 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1252,6 +1252,7 @@ struct brw_context * Gen6. See brw_update_null_renderbuffer_surface(). */ drm_intel_bo *multisampled_null_render_target_bo; + uint32_t fast_clear_op; } wm; diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index c3e93164c18..278cf17964c 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -246,6 +246,8 @@ upload_ps_state(struct brw_context *brw) ksp0 = brw->wm.base.prog_offset; } + dw4 |= brw->wm.fast_clear_op; + BEGIN_BATCH(8); OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); OUT_BATCH(ksp0); diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c index 49d4fe0e4f8..5e313bfd226 100644 --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c @@ -185,6 +185,8 @@ upload_ps_state(struct brw_context *brw) else dw6 |= GEN7_PS_POSOFFSET_NONE; + dw6 |= brw->wm.fast_clear_op; + /* _NEW_MULTISAMPLE * In case of non 1x per sample shading, only one of SIMD8 and SIMD16 * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader |