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authorTopi Pohjolainen <topi.pohjolainen@intel.com>2014-01-21 10:31:10 +0200
committerTopi Pohjolainen <topi.pohjolainen@intel.com>2014-01-22 08:13:32 +0200
commit89347dd61b7271bcca450332454253128eb10d4e (patch)
tree8792dce60a3b2ee01c192a330bb256e1374dc971 /src/mesa
parent1032c33cb93f1e8839be0f743b81492c2ca87e39 (diff)
i965/blorp: patch jump counters also for endif
No known bugs fixed but this is now in line with fs-generator. No regresssions on IVB. Eric further explained that: "The endif jump, since it's forward, is just an optimization to have set right -- otherwise, the GPU will just step forward instruction by instruction until it hits something else that updates the per-channel PC." Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp_blit.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp6
2 files changed, 5 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index fc4f902beb6..e2c2562ffc0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -923,6 +923,8 @@ brw_blorp_blit_program::compile(struct brw_context *brw,
*/
render_target_write();
+ brw_set_uip_jip(&func);
+
if (unlikely(INTEL_DEBUG & DEBUG_BLORP)) {
printf("Native code for BLORP blit:\n");
brw_dump_compile(&func, dump_file, 0, func.next_insn_offset);
diff --git a/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp b/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp
index 8b0cac2aaa7..208959ab211 100644
--- a/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp
+++ b/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp
@@ -154,7 +154,7 @@ test_gen7_blend_scaled_msaa_8(struct brw_context *brw)
"0x00000340: (+f0) mov(16) g64<1>UD 7D { align1 WE_normal 1H };\n"
"0x00000350: cmp.e.f0(16) null g60<8,8,1>UD 7D { align1 WE_normal 1H switch };\n"
"0x00000360: (+f0) mov(16) g64<1>UD 1D { align1 WE_normal 1H };\n"
- "0x00000370: endif(16) 2 null 0x00000002UD { align1 WE_normal 1H switch };\n"
+ "0x00000370: endif(16) 50 null 0x00000032UD { align1 WE_normal 1H switch };\n"
"0x00000380: mov(16) g60<1>UD g64<8,8,1>UD { align1 WE_normal 1H };\n"
"0x00000390: mov(16) g114<1>UD g60<8,8,1>UD { align1 WE_normal 1H };\n"
"0x000003a0: mov(16) g116<1>UD g44<8,8,1>UD { align1 WE_normal 1H };\n"
@@ -188,7 +188,7 @@ test_gen7_blend_scaled_msaa_8(struct brw_context *brw)
"0x00000550: (+f0) mov(16) g64<1>UD 7D { align1 WE_normal 1H };\n"
"0x00000560: cmp.e.f0(16) null g60<8,8,1>UD 7D { align1 WE_normal 1H switch };\n"
"0x00000570: (+f0) mov(16) g64<1>UD 1D { align1 WE_normal 1H };\n"
- "0x00000580: endif(16) 2 null 0x00000002UD { align1 WE_normal 1H switch };\n"
+ "0x00000580: endif(16) 50 null 0x00000032UD { align1 WE_normal 1H switch };\n"
"0x00000590: mov(16) g60<1>UD g64<8,8,1>UD { align1 WE_normal 1H };\n"
"0x000005a0: mov(16) g114<1>UD g60<8,8,1>UD { align1 WE_normal 1H };\n"
"0x000005b0: mov(16) g116<1>UD g44<8,8,1>UD { align1 WE_normal 1H };\n"
@@ -222,7 +222,7 @@ test_gen7_blend_scaled_msaa_8(struct brw_context *brw)
"0x00000760: (+f0) mov(16) g64<1>UD 7D { align1 WE_normal 1H };\n"
"0x00000770: cmp.e.f0(16) null g60<8,8,1>UD 7D { align1 WE_normal 1H switch };\n"
"0x00000780: (+f0) mov(16) g64<1>UD 1D { align1 WE_normal 1H };\n"
- "0x00000790: endif(16) 2 null 0x00000002UD { align1 WE_normal 1H switch };\n"
+ "0x00000790: endif(16) 50 null 0x00000032UD { align1 WE_normal 1H switch };\n"
"0x000007a0: mov(16) g60<1>UD g64<8,8,1>UD { align1 WE_normal 1H };\n"
"0x000007b0: mov(16) g114<1>UD g60<8,8,1>UD { align1 WE_normal 1H };\n"
"0x000007c0: mov(16) g116<1>UD g44<8,8,1>UD { align1 WE_normal 1H };\n"