diff options
| author | Rafael Antognolli <[email protected]> | 2017-08-29 16:30:26 -0700 |
|---|---|---|
| committer | Rafael Antognolli <[email protected]> | 2018-04-05 07:42:45 -0700 |
| commit | 7987d041fda0c98b243e540a46ac3a57a23cad26 (patch) | |
| tree | 4e0e91caa8bf8fa707359e01f2c427c3c47834b9 /src/mesa | |
| parent | 2efe8309d3dd44eb37dcf887f49fb3ce14746df8 (diff) | |
i965/surface_state: Emit the clear color address instead of value.
On Gen10, when emitting the surface state, use the value stored in the
clear color entry buffer by using a clear color address in the surface
state.
v4: Use the clear color offset from the clear_color_bo, when available.
Signed-off-by: Rafael Antognolli <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index ea855916403..3fb101bf68b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -187,6 +187,15 @@ brw_emit_surface_state(struct brw_context *brw, brw->isl_dev.ss.align, surf_offset); + bool use_clear_address = devinfo->gen >= 10 && aux_surf; + + struct brw_bo *clear_bo = NULL; + uint32_t clear_offset = 0; + if (use_clear_address) { + clear_bo = aux_buf->clear_color_bo; + clear_offset = aux_buf->clear_color_offset; + } + isl_surf_fill_state(&brw->isl_dev, state, .surf = &surf, .view = &view, .address = brw_state_reloc(&brw->batch, *surf_offset + brw->isl_dev.ss.addr_offset, @@ -195,6 +204,8 @@ brw_emit_surface_state(struct brw_context *brw, .aux_address = aux_offset, .mocs = brw_get_bo_mocs(devinfo, mt->bo), .clear_color = clear_color, + .use_clear_address = use_clear_address, + .clear_address = clear_offset, .x_offset_sa = tile_x, .y_offset_sa = tile_y); if (aux_surf) { /* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the @@ -224,6 +235,17 @@ brw_emit_surface_state(struct brw_context *brw, } } + + if (use_clear_address) { + /* Make sure the offset is aligned with a cacheline. */ + assert((clear_offset & 0x3f) == 0); + uint32_t *clear_address = + state + brw->isl_dev.ss.clear_color_state_offset; + *clear_address = brw_state_reloc(&brw->batch, + *surf_offset + + brw->isl_dev.ss.clear_color_state_offset, + clear_bo, *clear_address, reloc_flags); + } } static uint32_t |