diff options
| author | Francisco Jerez <[email protected]> | 2016-09-01 22:08:29 -0700 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2016-09-14 14:50:58 -0700 |
| commit | 3a74e437fdec02c28749c94bc1bcf21c3c4b48d7 (patch) | |
| tree | 4dc93eea1f16bffdaf9bf5ab292e4cc21f69bdce /src/mesa | |
| parent | 1bb5074474445ea9f54d0f52383f99ac0fa6128f (diff) | |
i965/vec4: Don't coalesce registers with overlapping writes not matching the MOV source.
In preparation for adding support for sub-GRF offsets to the VEC4 IR.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index d9dbc4c8543..8f8d2623416 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -1181,8 +1181,11 @@ vec4_visitor::opt_register_coalesce() break; } - /* This doesn't handle coalescing of multiple registers. */ - if (scan_inst->size_written > REG_SIZE) + /* This only handles coalescing of a single register starting at + * the source offset of the copy instruction. + */ + if (scan_inst->size_written > REG_SIZE || + scan_inst->dst.offset != inst->src[0].offset) break; /* Mark which channels we found unconditional writes for. */ @@ -1246,8 +1249,7 @@ vec4_visitor::opt_register_coalesce() while (scan_inst != inst) { if (scan_inst->dst.file == VGRF && scan_inst->dst.nr == inst->src[0].nr && - scan_inst->dst.offset / REG_SIZE == - inst->src[0].offset / REG_SIZE) { + scan_inst->dst.offset == inst->src[0].offset) { scan_inst->reswizzle(inst->dst.writemask, inst->src[0].swizzle); scan_inst->dst.file = inst->dst.file; |