diff options
author | Matt Turner <[email protected]> | 2015-10-01 10:06:55 -0700 |
---|---|---|
committer | Matt Turner <[email protected]> | 2015-10-05 12:06:33 -0700 |
commit | 36ea9922ada5ea99e54231697a4afb31d5f6b9bf (patch) | |
tree | 769fa04f9d9a8f63e5eec0e42968c080b4d55a00 /src/mesa | |
parent | 93161be9e7150ae5931000627833e714901cf195 (diff) |
mesa: Add missing _mm_mfence() before streaming loads.
According to the Intel Software Development Manual (Volume 1: Basic
Architecture, 12.10.3 Streaming Load Hint Instruction):
Streaming loads may be weakly ordered and may appear to software to
execute out of order with respect to other memory operations.
Software must explicitly use fences (e.g. MFENCE) if it needs to
preserve order among streaming loads or between streaming loads and
other memory operations.
That is, a memory fence is needed to preserve the order between the GPU
writing the buffer and the streaming loads reading it back.
Reported-by: Joseph Nuzman <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r-- | src/mesa/main/streaming-load-memcpy.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/main/streaming-load-memcpy.c b/src/mesa/main/streaming-load-memcpy.c index d7147afdc5c..32854b60eb2 100644 --- a/src/mesa/main/streaming-load-memcpy.c +++ b/src/mesa/main/streaming-load-memcpy.c @@ -59,6 +59,9 @@ _mesa_streaming_load_memcpy(void *restrict dst, void *restrict src, size_t len) len -= MIN2(bytes_before_alignment_boundary, len); } + if (len >= 64) + _mm_mfence(); + while (len >= 64) { __m128i *dst_cacheline = (__m128i *)d; __m128i *src_cacheline = (__m128i *)s; |