diff options
| author | Eric Anholt <[email protected]> | 2009-11-03 13:19:30 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2010-02-25 10:53:06 -0800 |
| commit | 719f2b1d8570aa58b970bd28941221ee6c34af9b (patch) | |
| tree | 8ac4eb21d80cafd612b89b0b8b0ebcb93c0241e3 /src/mesa | |
| parent | 554a8f4026459406e7d3ed4e7017a88a57492ddf (diff) | |
i965: Set up sandybridge depthbuffer.
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 21 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_decode.c | 4 |
3 files changed, 23 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index f708ee00632..d6eb6162df9 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -209,7 +209,14 @@ static void emit_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; struct intel_region *region = brw->state.depth_region; - unsigned int len = (intel->is_g4x || intel->is_ironlake) ? 6 : 5; + unsigned int len; + + if (intel->gen >= 6) + len = 7; + else if (intel->is_g4x || intel->is_ironlake) + len = 6; + else + len = 5; if (region == NULL) { BEGIN_BATCH(len); @@ -220,9 +227,12 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(0); - if (intel->is_g4x || intel->is_ironlake) + if (intel->is_g4x || intel->is_ironlake || intel->gen >= 6) OUT_BATCH(0); + if (intel->gen >= 6) + OUT_BATCH(0); + ADVANCE_BATCH(); } else { unsigned int format; @@ -243,6 +253,8 @@ static void emit_depthbuffer(struct brw_context *brw) } assert(region->tiling != I915_TILING_X); + if (IS_GEN6(intel->intelScreen->deviceID)) + assert(region->tiling != I915_TILING_NONE); BEGIN_BATCH(len); OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); @@ -259,9 +271,12 @@ static void emit_depthbuffer(struct brw_context *brw) ((region->height - 1) << 19)); OUT_BATCH(0); - if (intel->is_g4x || intel->is_ironlake) + if (intel->is_g4x || intel->is_ironlake || intel->gen >= 6) OUT_BATCH(0); + if (intel->gen >= 6) + OUT_BATCH(0); + ADVANCE_BATCH(); } } diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 1ee4f4ab80b..4c12e68c0e2 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -143,9 +143,11 @@ const struct brw_tracked_state *gen6_atoms[] = &brw_binding_table_pointers, &brw_blend_constant_color, +#endif &brw_depthbuffer, +#if 0 &brw_polygon_stipple, &brw_polygon_stipple_offset, diff --git a/src/mesa/drivers/dri/intel/intel_decode.c b/src/mesa/drivers/dri/intel/intel_decode.c index a9dfe281cbd..c3112d980ab 100644 --- a/src/mesa/drivers/dri/intel/intel_decode.c +++ b/src/mesa/drivers/dri/intel/intel_decode.c @@ -1592,7 +1592,7 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) return len; case 0x7905: - if (len != 5 && len != 6) + if (len < 5 || len > 7) fprintf(out, "Bad count in 3DSTATE_DEPTH_BUFFER\n"); if (count < len) BUFFER_FAIL(count, len, "3DSTATE_DEPTH_BUFFER"); @@ -1611,6 +1611,8 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) instr_out(data, hw_offset, 4, "volume depth\n"); if (len == 6) instr_out(data, hw_offset, 5, "\n"); + if (len == 7) + instr_out(data, hw_offset, 6, "render target view extent\n"); return len; |