diff options
author | Eric Anholt <[email protected]> | 2011-08-09 11:00:28 -0700 |
---|---|---|
committer | Eric Anholt <[email protected]> | 2011-08-16 13:04:43 -0700 |
commit | 250770b74d33bb8625c780a74a89477af033d13a (patch) | |
tree | 3f64809914f53e516c75e8c77ed0037c405baae9 /src/mesa | |
parent | 6408b0295f5c8be6fea891a025d79752484721b6 (diff) |
i965/vs: Respect the gen6 limitation that math opcodes can't be align16.
Fixes vs-acos-vec3 and friends.
Diffstat (limited to 'src/mesa')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 9 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 26 |
2 files changed, 33 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp index 21830f99fc2..effc82a8004 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp @@ -250,6 +250,14 @@ vec4_visitor::generate_math1_gen6(vec4_instruction *inst, struct brw_reg dst, struct brw_reg src) { + /* Can't do writemask because math can't be align16. */ + assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); + /* Source swizzles are ignored. */ + assert(!src.abs); + assert(!src.negate); + assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW); + + brw_set_access_mode(p, BRW_ALIGN_1); brw_math(p, dst, brw_math_function(inst->opcode), @@ -258,6 +266,7 @@ vec4_visitor::generate_math1_gen6(vec4_instruction *inst, src, BRW_MATH_DATA_SCALAR, BRW_MATH_PRECISION_FULL); + brw_set_access_mode(p, BRW_ALIGN_16); } void diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index fde1d67759a..f4756a9a1a8 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -129,7 +129,18 @@ vec4_visitor::emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src) src_reg temp_src = src_reg(this, glsl_type::vec4_type); emit(BRW_OPCODE_MOV, dst_reg(temp_src), src); - emit(opcode, dst, temp_src); + if (dst.writemask != WRITEMASK_XYZW) { + /* The gen6 math instruction must be align1, so we can't do + * writemasks. + */ + dst_reg temp_dst = dst_reg(this, glsl_type::vec4_type); + + emit(opcode, temp_dst, temp_src); + + emit(BRW_OPCODE_MOV, dst, src_reg(temp_dst)); + } else { + emit(opcode, dst, temp_src); + } } void @@ -184,7 +195,18 @@ vec4_visitor::emit_math2_gen6(enum opcode opcode, emit(BRW_OPCODE_MOV, dst, src1); src1 = expanded; - emit(opcode, dst, src0, src1); + if (dst.writemask != WRITEMASK_XYZW) { + /* The gen6 math instruction must be align1, so we can't do + * writemasks. + */ + dst_reg temp_dst = dst_reg(this, glsl_type::vec4_type); + + emit(opcode, temp_dst, src0, src1); + + emit(BRW_OPCODE_MOV, dst, src_reg(temp_dst)); + } else { + emit(opcode, dst, src0, src1); + } } void |