i965/gs: Update defines related to GS surface organization.

Defines that previously referred to VS now refer to VEC4, since they
will be shared by the user-programmable vertex shader and geometry
shader stages.

Defines that previously referred to the Gen6 geometry shader stage
(which is only used for transform feedback) are now renamed to
explicitly refer to Gen6, to avoid confusion with the Gen7
user-programmable geometry shader stage.

Based on work by Eric Anholt <[email protected]>.

Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Chad Versace <[email protected]>

8 files changed, 29 insertions, 29 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 13daf1e20b0..dcd4c9ac701 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -615,10 +615,10 @@ struct brw_gs_prog_data
  *    |  36 | UBO 11                  |
  *    +-------------------------------+
  *
- * Our VS binding tables are programmed as follows:
+ * Our VS (and Gen7 GS) binding tables are programmed as follows:
  *
  *    +-----+-------------------------+
- *    |   0 | VS Pull Constant Buffer |
+ *    |   0 | Pull Constant Buffer    |
  *    +-----+-------------------------+
  *    |   1 | Texture 0               |
  *    |   . |     .                   |
@@ -648,14 +648,14 @@ struct brw_gs_prog_data
 /** Maximum size of the binding table. */
 #define BRW_MAX_WM_SURFACES          (SURF_INDEX_WM_SHADER_TIME + 1)
 
-#define SURF_INDEX_VERT_CONST_BUFFER (0)
-#define SURF_INDEX_VS_TEXTURE(t)     (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
-#define SURF_INDEX_VS_UBO(u)         (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u)
-#define SURF_INDEX_VS_SHADER_TIME    (SURF_INDEX_VS_UBO(12))
-#define BRW_MAX_VS_SURFACES          (SURF_INDEX_VS_SHADER_TIME + 1)
+#define SURF_INDEX_VEC4_CONST_BUFFER (0)
+#define SURF_INDEX_VEC4_TEXTURE(t)   (SURF_INDEX_VEC4_CONST_BUFFER + 1 + (t))
+#define SURF_INDEX_VEC4_UBO(u)       (SURF_INDEX_VEC4_TEXTURE(BRW_MAX_TEX_UNIT) + u)
+#define SURF_INDEX_VEC4_SHADER_TIME  (SURF_INDEX_VEC4_UBO(12))
+#define BRW_MAX_VEC4_SURFACES        (SURF_INDEX_VEC4_SHADER_TIME + 1)
 
-#define SURF_INDEX_SOL_BINDING(t)    ((t))
-#define BRW_MAX_GS_SURFACES          SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
+#define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
+#define BRW_MAX_GEN6_GS_SURFACES       SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
 
 /**
  * Stride in bytes between shader_time entries.
@@ -1153,7 +1153,7 @@ struct brw_context
       int push_const_size; /* in 256-bit register increments */
 
       uint32_t bind_bo_offset;
-      uint32_t surf_offset[BRW_MAX_VS_SURFACES];
+      uint32_t surf_offset[BRW_MAX_VEC4_SURFACES];
 
       /** SAMPLER_STATE count and table offset */
       uint32_t sampler_count;
@@ -1173,7 +1173,7 @@ struct brw_context
       uint32_t state_offset;
 
       uint32_t bind_bo_offset;
-      uint32_t surf_offset[BRW_MAX_GS_SURFACES];
+      uint32_t surf_offset[BRW_MAX_GEN6_GS_SURFACES];
    } ff_gs;
 
    struct {
diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c
index 7fff53e5c4c..2c94eb0809c 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c
@@ -436,7 +436,7 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
                           final_write ? c->reg.temp : brw_null_reg(), /* dest */
                           1, /* msg_reg_nr */
                           c->reg.header, /* src0 */
-                          SURF_INDEX_SOL_BINDING(binding), /* binding_table_index */
+                          SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
                           final_write); /* send_commit_msg */
          }
       }
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 1f002605e8f..bf04bd9881e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -155,7 +155,7 @@ vec4_generator::~vec4_generator()
 void
 vec4_generator::mark_surface_used(unsigned surf_index)
 {
-   assert(surf_index < BRW_MAX_VS_SURFACES);
+   assert(surf_index < BRW_MAX_VEC4_SURFACES);
 
    prog_data->binding_table_size = MAX2(prog_data->binding_table_size,
                                         surf_index + 1);
@@ -386,7 +386,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 	      dst,
 	      inst->base_mrf,
 	      src,
-	      SURF_INDEX_VS_TEXTURE(inst->sampler),
+	      SURF_INDEX_VEC4_TEXTURE(inst->sampler),
 	      inst->sampler,
 	      msg_type,
 	      1, /* response length */
@@ -395,7 +395,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 	      BRW_SAMPLER_SIMD_MODE_SIMD4X2,
 	      return_format);
 
-   mark_surface_used(SURF_INDEX_VS_TEXTURE(inst->sampler));
+   mark_surface_used(SURF_INDEX_VEC4_TEXTURE(inst->sampler));
 }
 
 void
@@ -1004,8 +1004,8 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
       break;
 
    case SHADER_OPCODE_SHADER_TIME_ADD:
-      brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
-      mark_surface_used(SURF_INDEX_VS_SHADER_TIME);
+      brw_shader_time_add(p, src[0], SURF_INDEX_VEC4_SHADER_TIME);
+      mark_surface_used(SURF_INDEX_VEC4_SHADER_TIME);
       break;
 
    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 68e0cb96972..6771630d30c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1675,7 +1675,7 @@ vec4_visitor::visit(ir_expression *ir)
       src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
       packed_consts.type = result.type;
       src_reg surf_index =
-         src_reg(SURF_INDEX_VS_UBO(uniform_block->value.u[0]));
+         src_reg(SURF_INDEX_VEC4_UBO(uniform_block->value.u[0]));
       if (const_offset_ir) {
          offset = src_reg(const_offset / 16);
       } else {
@@ -3099,7 +3099,7 @@ vec4_visitor::emit_pull_constant_load(vec4_instruction *inst,
 				      int base_offset)
 {
    int reg_offset = base_offset + orig_src.reg_offset;
-   src_reg index = src_reg((unsigned)SURF_INDEX_VERT_CONST_BUFFER);
+   src_reg index = src_reg((unsigned)SURF_INDEX_VEC4_CONST_BUFFER);
    src_reg offset = get_pull_constant_offset(inst, orig_src.reladdr, reg_offset);
    vec4_instruction *load;
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
index 1787df8f25d..d2dc2536be2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
@@ -560,7 +560,7 @@ vec4_vs_visitor::get_vp_src_reg(const prog_src_register &src)
       #endif
 
          result = src_reg(this, glsl_type::vec4_type);
-         src_reg surf_index = src_reg(unsigned(SURF_INDEX_VERT_CONST_BUFFER));
+         src_reg surf_index = src_reg(unsigned(SURF_INDEX_VEC4_CONST_BUFFER));
          vec4_instruction *load =
             new(mem_ctx) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD,
                                           dst_reg(result), surf_index, reladdr);
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index 4577e769122..fe2459f09e5 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -59,7 +59,7 @@ brw_upload_vs_pull_constants(struct brw_context *brw)
       if (brw->vs.const_bo) {
 	 drm_intel_bo_unreference(brw->vs.const_bo);
 	 brw->vs.const_bo = NULL;
-	 brw->vs.surf_offset[SURF_INDEX_VERT_CONST_BUFFER] = 0;
+	 brw->vs.surf_offset[SURF_INDEX_VEC4_CONST_BUFFER] = 0;
 	 brw->state.dirty.brw |= BRW_NEW_VS_CONSTBUF;
       }
       return;
@@ -89,7 +89,7 @@ brw_upload_vs_pull_constants(struct brw_context *brw)
 
    drm_intel_gem_bo_unmap_gtt(brw->vs.const_bo);
 
-   const int surf = SURF_INDEX_VERT_CONST_BUFFER;
+   const int surf = SURF_INDEX_VEC4_CONST_BUFFER;
    brw->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0, size,
                                      &brw->vs.surf_offset[surf], false);
 
@@ -116,7 +116,7 @@ brw_upload_vs_ubo_surfaces(struct brw_context *brw)
       return;
 
    brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_VERTEX],
-			   &brw->vs.surf_offset[SURF_INDEX_VS_UBO(0)]);
+			   &brw->vs.surf_offset[SURF_INDEX_VEC4_UBO(0)]);
 }
 
 const struct brw_tracked_state brw_vs_ubo_surfaces = {
@@ -139,7 +139,7 @@ brw_vs_upload_binding_table(struct brw_context *brw)
    int i;
 
    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
-      gen7_create_shader_time_surface(brw, &brw->vs.surf_offset[SURF_INDEX_VS_SHADER_TIME]);
+      gen7_create_shader_time_surface(brw, &brw->vs.surf_offset[SURF_INDEX_VEC4_SHADER_TIME]);
    }
 
    /* CACHE_NEW_VS_PROG: Skip making a binding table if we don't use textures or
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 8bc3938bb26..ea433caaa2d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -754,7 +754,7 @@ brw_update_texture_surfaces(struct brw_context *brw)
    unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
 
    for (unsigned s = 0; s < num_samplers; s++) {
-      brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
+      brw->vs.surf_offset[SURF_INDEX_VEC4_TEXTURE(s)] = 0;
       brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
 
       if (vs->SamplersUsed & (1 << s)) {
@@ -764,7 +764,7 @@ brw_update_texture_surfaces(struct brw_context *brw)
          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
             brw->vtbl.update_texture_surface(ctx, unit,
                                              brw->vs.surf_offset,
-                                             SURF_INDEX_VS_TEXTURE(s));
+                                             SURF_INDEX_VEC4_TEXTURE(s));
          }
       }
 
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c
index ced9bb90736..21da444247f 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -48,7 +48,7 @@ gen6_update_sol_surfaces(struct brw_context *brw)
    int i;
 
    for (i = 0; i < BRW_MAX_SOL_BINDINGS; ++i) {
-      const int surf_index = SURF_INDEX_SOL_BINDING(i);
+      const int surf_index = SURF_INDEX_GEN6_SOL_BINDING(i);
       if (_mesa_is_xfb_active_and_unpaused(ctx) &&
           i < linked_xfb_info->NumOutputs) {
          unsigned buffer = linked_xfb_info->Outputs[i].OutputBuffer;
@@ -112,11 +112,11 @@ brw_gs_upload_binding_table(struct brw_context *brw)
     * space for the binding table.
     */
    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
-			  sizeof(uint32_t) * BRW_MAX_GS_SURFACES,
+			  sizeof(uint32_t) * BRW_MAX_GEN6_GS_SURFACES,
 			  32, &brw->ff_gs.bind_bo_offset);
 
    /* BRW_NEW_SURFACES */
-   memcpy(bind, brw->ff_gs.surf_offset, BRW_MAX_GS_SURFACES * sizeof(uint32_t));
+   memcpy(bind, brw->ff_gs.surf_offset, BRW_MAX_GEN6_GS_SURFACES * sizeof(uint32_t));
 
    brw->state.dirty.brw |= BRW_NEW_GS_BINDING_TABLE;
 }