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authorAnuj Phogat <[email protected]>2015-07-09 10:47:17 -0700
committerAnuj Phogat <[email protected]>2015-09-28 12:43:43 -0700
commitbbbc9fd8e5e2a4434c8630eacd7943d59aa73c47 (patch)
treea57af5b254b644fa34e3732af1329753149e0826 /src/mesa
parent1dc41be9ebd07825836b0ca4b98e00ffc7ecc0ec (diff)
i965: Use helper function intel_get_tile_dims() in surface setup
It takes care of using the correct tile width if we later use other tiling patterns for aux miptree. V2: Remove the comment about using Yf for aux miptree. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/gen8_surface_state.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index d2f333fd4dd..c5f1bae8ecb 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -276,8 +276,13 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
}
if (aux_mt) {
+ uint32_t tile_w, tile_h;
+ assert(aux_mt->tiling == I915_TILING_Y);
+ intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode,
+ aux_mt->cpp, &tile_w, &tile_h);
surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
- SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
+ SET_FIELD((aux_mt->pitch / tile_w) - 1,
+ GEN8_SURFACE_AUX_PITCH) |
aux_mode;
} else {
surf[6] = 0;
@@ -501,8 +506,13 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
}
if (aux_mt) {
+ uint32_t tile_w, tile_h;
+ assert(aux_mt->tiling == I915_TILING_Y);
+ intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode,
+ aux_mt->cpp, &tile_w, &tile_h);
surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
- SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
+ SET_FIELD((aux_mt->pitch / tile_w) - 1,
+ GEN8_SURFACE_AUX_PITCH) |
aux_mode;
} else {
surf[6] = 0;