diff options
| author | Xiang, Haihao <[email protected]> | 2008-12-18 10:07:45 +0800 |
|---|---|---|
| committer | Xiang, Haihao <[email protected]> | 2008-12-18 10:07:45 +0800 |
| commit | df73363ed1aa34cc0dc5feefb3933309591fa015 (patch) | |
| tree | e5b204806fda47d3b7208ea905b8282a3e775311 /src/mesa | |
| parent | 35aebf46679a6450b912b592b83badcfb523b79c (diff) | |
i915: fix abort issue. (bug #19147)
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i915/i830_vtbl.c | 15 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/i915_vtbl.c | 13 |
2 files changed, 24 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index 3b3ff2bceda..8fc8aa5f900 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -297,7 +297,7 @@ i830_emit_invarient_state(struct intel_context *intel) { BATCH_LOCALS; - BEGIN_BATCH(40, IGNORE_CLIPRECTS); + BEGIN_BATCH(30, IGNORE_CLIPRECTS); OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); OUT_BATCH(0); @@ -491,8 +491,17 @@ i830_emit_state(struct intel_context *intel) } if (dirty & I830_UPLOAD_BUFFERS) { + GLuint count = 9; + DBG("I830_UPLOAD_BUFFERS:\n"); - BEGIN_BATCH(I830_DEST_SETUP_SIZE + 2, IGNORE_CLIPRECTS); + + if (state->depth_region) + count += 3; + + if (intel->constant_cliprect) + count += 6; + + BEGIN_BATCH(count, IGNORE_CLIPRECTS); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]); OUT_RELOC(state->draw_region->buffer, @@ -557,6 +566,8 @@ i830_emit_state(struct intel_context *intel) OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S4]); OUT_BATCH(state->Tex[i][I830_TEXREG_MCS]); OUT_BATCH(state->Tex[i][I830_TEXREG_CUBE]); + + ADVANCE_BATCH(); } if (dirty & I830_UPLOAD_TEXBLEND(i)) { diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index e79c955d64d..3f6d282d342 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -173,7 +173,7 @@ i915_emit_invarient_state(struct intel_context *intel) { BATCH_LOCALS; - BEGIN_BATCH(200, IGNORE_CLIPRECTS); + BEGIN_BATCH(20, IGNORE_CLIPRECTS); OUT_BATCH(_3DSTATE_AA_CMD | AA_LINE_ECAAR_WIDTH_ENABLE | @@ -376,9 +376,18 @@ i915_emit_state(struct intel_context *intel) } if (dirty & I915_UPLOAD_BUFFERS) { + GLuint count = 9; + if (INTEL_DEBUG & DEBUG_STATE) fprintf(stderr, "I915_UPLOAD_BUFFERS:\n"); - BEGIN_BATCH(I915_DEST_SETUP_SIZE + 2, IGNORE_CLIPRECTS); + + if (state->depth_region) + count += 3; + + if (intel->constant_cliprect) + count += 6; + + BEGIN_BATCH(count, IGNORE_CLIPRECTS); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]); OUT_RELOC(state->draw_region->buffer, |