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authorTopi Pohjolainen <[email protected]>2017-01-10 10:24:26 +0200
committerTopi Pohjolainen <[email protected]>2017-01-27 08:57:26 +0200
commitb13d30a72ba06187ba7398c1a56c34980a021005 (patch)
tree53400abc8b270ef11b981fa891056f9e80642511 /src/mesa
parentb864e3d7eee82accf3430b46d5a9269323fe0ba0 (diff)
i965/blorp/gen6: Remove dead code in hiz setup
Such as comment states for intel_miptree_hiz_buffer::mt, hiz_mt only exists for gen6. In addition, intel_hiz_miptree_buf_create() uses MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD unconditionally. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index f21b41a4e3b..52f85ff0677 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -250,15 +250,15 @@ blorp_surf_for_miptree(struct brw_context *brw,
struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
if (hiz_mt) {
- if (brw->gen == 6 &&
- hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
- /* gen6 requires the HiZ buffer to be manually offset to the
- * right location. We could fixup the surf but it doesn't
- * matter since most of those fields don't matter.
- */
- apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
- &surf->aux_addr.offset);
- }
+ assert(brw->gen == 6 &&
+ hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
+
+ /* gen6 requires the HiZ buffer to be manually offset to the
+ * right location. We could fixup the surf but it doesn't
+ * matter since most of those fields don't matter.
+ */
+ apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
+ &surf->aux_addr.offset);
assert(hiz_mt->pitch == aux_surf->row_pitch);
}
}