diff options
| author | Kenneth Graunke <[email protected]> | 2013-11-25 13:53:33 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-12-09 13:52:18 -0800 |
| commit | 19190c2b8c67baa258cf2865ea95ff5dca300d36 (patch) | |
| tree | d4e0eb369e6bcdd9aad98fb1f7aae03494c145a7 /src/mesa | |
| parent | 088494aa032bf32db8b67f1fb07e5797603a473d (diff) | |
i965: Replace OUT_RELOC_FENCED with OUT_RELOC.
On Gen4+, OUT_RELOC_FENCED is equivalent to OUT_RELOC; libdrm silently
ignores the fenced flag:
/* We never use HW fences for rendering on 965+ */
if (bufmgr_gem->gen >= 4)
need_fence = false;
Thanks to Eric for noticing this.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.h | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_blit.c | 22 |
2 files changed, 10 insertions, 16 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h index 02120bbcc3b..80cd571fe13 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h @@ -173,10 +173,6 @@ void intel_batchbuffer_cached_advance(struct brw_context *brw); intel_batchbuffer_emit_reloc(brw, buf, \ read_domains, write_domain, delta); \ } while (0) -#define OUT_RELOC_FENCED(buf, read_domains, write_domain, delta) do { \ - intel_batchbuffer_emit_reloc_fenced(brw, buf, \ - read_domains, write_domain, delta); \ -} while (0) #define ADVANCE_BATCH() intel_batchbuffer_advance(brw); #define CACHED_BATCH() intel_batchbuffer_cached_advance(brw); diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index ba902ac5bc4..7bc289f350e 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -378,14 +378,12 @@ intelEmitCopyBlit(struct brw_context *brw, OUT_BATCH(BR13 | (uint16_t)dst_pitch); OUT_BATCH((dst_y << 16) | dst_x); OUT_BATCH((dst_y2 << 16) | dst_x2); - OUT_RELOC_FENCED(dst_buffer, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - dst_offset); + OUT_RELOC(dst_buffer, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + dst_offset); OUT_BATCH((src_y << 16) | src_x); OUT_BATCH((uint16_t)src_pitch); - OUT_RELOC_FENCED(src_buffer, - I915_GEM_DOMAIN_RENDER, 0, - src_offset); + OUT_RELOC(src_buffer, I915_GEM_DOMAIN_RENDER, 0, src_offset); ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled); @@ -449,9 +447,9 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, OUT_BATCH(br13); OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ - OUT_RELOC_FENCED(dst_buffer, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - dst_offset); + OUT_RELOC(dst_buffer, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + dst_offset); OUT_BATCH(0); /* bg */ OUT_BATCH(fg_color); /* fg */ OUT_BATCH(0); /* pattern base addr */ @@ -568,9 +566,9 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw, OUT_BATCH(BR13); OUT_BATCH((y << 16) | x); OUT_BATCH(((y + height) << 16) | (x + width)); - OUT_RELOC_FENCED(region->bo, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - 0); + OUT_RELOC(region->bo, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + 0); OUT_BATCH(0xffffffff); /* white, but only alpha gets written */ ADVANCE_BATCH_TILED(dst_y_tiled, false); |