diff options
| author | Zhenyu Wang <[email protected]> | 2010-09-17 14:47:05 +0800 |
|---|---|---|
| committer | Zhenyu Wang <[email protected]> | 2010-09-28 15:58:20 +0800 |
| commit | 9c39a9fcb2c76897e9b5aff68ce197a411c4e25c (patch) | |
| tree | bdaa0d79880e6574a897545e7409c8e87bb0d922 /src/mesa | |
| parent | 7401a98e29eaaa80fc42e18b126988683b090543 (diff) | |
i965: VS use SPF mode on sandybridge for now
Until conditional instructions were fixed, use SPF mode instead for now.
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vs_emit.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_vs_state.c | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 162ddc93c8b..8ac979dceaa 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1635,6 +1635,10 @@ void brw_vs_emit(struct brw_vs_compile *c ) printf("\n"); } + /* FIXME Need to fix conditional instruction to remove this */ + if (intel->gen >= 6) + p->single_program_flow = GL_TRUE; + brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_set_access_mode(p, BRW_ALIGN_16); if_depth_in_loop[loop_depth] = 0; diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index 4080a9dedfd..50047a33a87 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -93,7 +93,7 @@ upload_vs_state(struct brw_context *brw) BEGIN_BATCH(6); OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2)); OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); - OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) | + OUT_BATCH(GEN6_VS_SPF_MODE | (0 << GEN6_VS_SAMPLER_COUNT_SHIFT) | (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); OUT_BATCH(0); /* scratch space base offset */ OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) | |