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authorEric Anholt <[email protected]>2013-04-13 01:46:09 -0700
committerEric Anholt <[email protected]>2013-04-21 12:28:04 -0700
commit47c0b5ecdd14ab5b07e4d3016e8dff7c9c3abb8b (patch)
treef2ea5c4e3860d6fd7911b50d4440f3fda6807163 /src/mesa
parent1842dd08b83269816fe8eb8f2dcc1252f606fe48 (diff)
mesa: Introduce a globally-available minify() macro.
This matches u_minify()'s behavior, for consistency. Reviewed-by: Brian Paul <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i915/i915_tex_layout.c18
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c8
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_layout.c12
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_layout.h6
-rw-r--r--src/mesa/drivers/dri/nouveau/nouveau_texture.c4
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c9
-rw-r--r--src/mesa/main/macros.h6
7 files changed, 27 insertions, 36 deletions
diff --git a/src/mesa/drivers/dri/i915/i915_tex_layout.c b/src/mesa/drivers/dri/i915/i915_tex_layout.c
index 90911a647c7..8be601b9296 100644
--- a/src/mesa/drivers/dri/i915/i915_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/i915_tex_layout.c
@@ -172,9 +172,9 @@ i915_miptree_layout_3d(struct intel_mipmap_tree * mt)
stack_height += MAX2(2, height);
- width = minify(width);
- height = minify(height);
- depth = minify(depth);
+ width = minify(width, 1);
+ height = minify(height, 1);
+ depth = minify(depth, 1);
}
/* Fixup depth image_offsets: */
@@ -186,7 +186,7 @@ i915_miptree_layout_3d(struct intel_mipmap_tree * mt)
0, i * stack_height);
}
- depth = minify(depth);
+ depth = minify(depth, 1);
}
/* Multiply slice size by texture depth for total size. It's
@@ -219,8 +219,8 @@ i915_miptree_layout_2d(struct intel_mipmap_tree * mt)
mt->total_height += img_height;
- width = minify(width);
- height = minify(height);
+ width = minify(width, 1);
+ height = minify(height, 1);
}
}
@@ -447,9 +447,9 @@ i945_miptree_layout_3d(struct intel_mipmap_tree * mt)
pack_y_pitch >>= 1;
}
- width = minify(width);
- height = minify(height);
- depth = minify(depth);
+ width = minify(width, 1);
+ height = minify(height, 1);
+ depth = minify(depth, 1);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index d28e5aff009..f0736fa976f 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -48,7 +48,7 @@ brw_miptree_layout_texture_array(struct intel_context *intel,
int h0, h1, q;
h0 = ALIGN(mt->physical_height0, mt->align_h);
- h1 = ALIGN(minify(mt->physical_height0), mt->align_h);
+ h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h);
if (mt->array_spacing_lod0)
qpitch = h0;
else
@@ -131,10 +131,10 @@ brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
mt->total_height += y;
- width = minify(width);
- height = minify(height);
+ width = minify(width, 1);
+ height = minify(height, 1);
if (mt->target == GL_TEXTURE_3D)
- depth = minify(depth);
+ depth = minify(depth, 1);
if (mt->compressed) {
pack_y_pitch = (height + 3) / 4;
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index 59d4bc319fe..fbb6520e7a1 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -170,11 +170,11 @@ void i945_miptree_layout_2d(struct intel_mipmap_tree *mt)
GLuint mip1_width;
if (mt->compressed) {
- mip1_width = ALIGN(minify(mt->physical_width0), mt->align_w)
- + ALIGN(minify(minify(mt->physical_width0)), mt->align_w);
+ mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
+ ALIGN(minify(mt->physical_width0, 2), mt->align_w);
} else {
- mip1_width = ALIGN(minify(mt->physical_width0), mt->align_w)
- + minify(minify(mt->physical_width0));
+ mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
+ minify(mt->physical_width0, 2);
}
if (mip1_width > mt->total_width) {
@@ -208,7 +208,7 @@ void i945_miptree_layout_2d(struct intel_mipmap_tree *mt)
y += img_height;
}
- width = minify(width);
- height = minify(height);
+ width = minify(width, 1);
+ height = minify(height, 1);
}
}
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.h b/src/mesa/drivers/dri/intel/intel_tex_layout.h
index 12ed16d8216..f353cf4eb43 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.h
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.h
@@ -32,12 +32,6 @@
#include "main/macros.h"
-
-static INLINE GLuint minify( GLuint d )
-{
- return MAX2(1, d>>1);
-}
-
extern void i945_miptree_layout_2d(struct intel_mipmap_tree *mt);
void
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_texture.c b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
index 64cd23b3851..4e3c26bab87 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_texture.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
@@ -411,8 +411,8 @@ relayout_texture(struct gl_context *ctx, struct gl_texture_object *t)
};
offset += size;
- width = MAX2(1, width / 2);
- height = MAX2(1, height / 2);
+ width = minify(width, 1);
+ height = minify(height, 1);
}
/* Get new storage. */
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index b0c49baf2b3..ebf6a194cc9 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -147,15 +147,6 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
lvl->rowstride, lvl->width, height, lvl->faces[face].offset);
}
-static GLuint minify(GLuint size, GLuint levels)
-{
- size = size >> levels;
- if (size < 1)
- size = 1;
- return size;
-}
-
-
static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
{
GLuint curOffset, i, face, level;
diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
index f6d38fb6480..b206acacf4a 100644
--- a/src/mesa/main/macros.h
+++ b/src/mesa/main/macros.h
@@ -656,6 +656,12 @@ INTERP_4F(GLfloat t, GLfloat dst[4], const GLfloat out[4], const GLfloat in[4])
#define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C))
#define MAX3( A, B, C ) ((A) > (B) ? MAX2(A, C) : MAX2(B, C))
+static inline unsigned
+minify(unsigned value, unsigned levels)
+{
+ return MAX2(1, value >> levels);
+}
+
/**
* Align a value up to an alignment value
*