diff options
| author | Anuj Phogat <[email protected]> | 2018-10-11 10:52:16 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-11-26 15:11:36 -0800 |
| commit | 3ce04da5b4c95c4789afd4eea51fb276b8eb9dfa (patch) | |
| tree | 75e93766e6ff0ac289375f13e573a5809ff3213e /src/mesa | |
| parent | 3282c7be899f34cd6d2fe695976383c949e1c6c2 (diff) | |
i965/icl: Set use full ways in L3CNTLREG
L3 allocation table in h/w specification recommends using 4 KB
granularity for programming allocation fields in L3CNTLREG.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_l3_state.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 897c91aa31e..aec27a10ec4 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1647,6 +1647,7 @@ enum brw_pixel_shader_coverage_mask_mode { # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT 25 # define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25) # define GEN8_L3CNTLREG_EDBC_NO_HANG (1 << 9) +# define GEN11_L3CNTLREG_USE_FULL_WAYS (1 << 10) #define GEN10_CACHE_MODE_SS 0x0e420 #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4) diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c index 8c6c4c47481..3ee13d1e39f 100644 --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c @@ -119,6 +119,7 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg) assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]); const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) | + (devinfo->gen == 11 ? GEN11_L3CNTLREG_USE_FULL_WAYS : 0) | SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) | SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) | SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) | |