diff options
| author | Eric Anholt <[email protected]> | 2019-09-05 16:04:01 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2019-10-20 04:39:48 +0000 |
| commit | 2a548cf92f53a5e1ab158605d30e61cc8aa73ecf (patch) | |
| tree | 31cb79bc45c1fd9dc2fa8ef0ec258279429635b1 /src/mesa | |
| parent | ecddabfa76aeac282c1a5c365708cd0a79e3b80d (diff) | |
radeon: Fill in the TXOFFSET field containing the tile bits in our relocs.
The first arg to OUT_BATCH_RELOC is ignored, we actually wanted these
in the third arg. They're always 0 so far, so it didn't matter.
v2: Reword commit message that I don't end up using the tile bits, but
keep the commit as a cleanup anyway.
Reviewed-by: Marek Olšák <[email protected]> (v1)
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/r200/r200_state_init.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_state_init.c | 5 |
2 files changed, 5 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 41c3df710e5..b2f661e3881 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -581,11 +581,11 @@ static void tex_emit_mm(struct gl_context *ctx, struct radeon_state_atom *atom) if (dwords > atom->cmd_size) { OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0)); if (t->mt && !t->image_override) { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, t->tile_bits, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } else { if (t->bo) - OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, + OUT_BATCH_RELOC(t->tile_bits, t->bo, t->tile_bits, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } } diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 6a8cf606dcb..c1f00ba9ec7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -488,12 +488,13 @@ static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } else { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t), + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, + get_base_teximage_offset(t) | t->tile_bits, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } } else { if (t->bo) - OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, + OUT_BATCH_RELOC(t->tile_bits, t->bo, t->tile_bits, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } } |