diff options
| author | Jason Ekstrand <[email protected]> | 2020-01-17 12:09:13 -0600 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2020-01-30 18:46:20 -0600 |
| commit | 09e4c33085f15ffa691053143bec9dbf4aecfeaa (patch) | |
| tree | 1376b46f1317594340045cefef1d5c7e2663a880 /src/mesa | |
| parent | 73a684964b392c4df84373e8419e355267d57ff5 (diff) | |
intel/blorp: Always emit URB config on Gen7+
Previously, i965/iris tried to reuse the currently programmed URB config
if it was good enough for BLORP, rather than reprogramming it each time.
However, this will make some things harder on Gen12+ and we've not seen
any performance impact from emitting URB more frequently in ANV.
This makes the blorp <-> driver interface a bit simpler on Gen7+ because
now all the driver has to do is to provide the L3$ config rather than
trying to hand off URB re-config to blorp.
Cc: "20.0" [email protected]
Reviewed-by: Kenneth Graunke <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/genX_blorp_exec.c | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c index 8769602547e..1d7f89e6c32 100644 --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c @@ -231,8 +231,7 @@ blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch, #endif } -#if GEN_GEN >= 8 -static struct blorp_address +UNUSED static struct blorp_address blorp_get_workaround_page(struct blorp_batch *batch) { assert(batch->blorp->driver_ctx == batch->driver_batch); @@ -242,7 +241,6 @@ blorp_get_workaround_page(struct blorp_batch *batch) .buffer = brw->workaround_bo, }; } -#endif static void blorp_flush_range(UNUSED struct blorp_batch *batch, UNUSED void *start, @@ -253,6 +251,16 @@ blorp_flush_range(UNUSED struct blorp_batch *batch, UNUSED void *start, */ } +#if GEN_GEN >= 7 +static const struct gen_l3_config * +blorp_get_l3_config(struct blorp_batch *batch) +{ + assert(batch->blorp->driver_ctx == batch->driver_batch); + struct brw_context *brw = batch->driver_batch; + + return brw->l3.config; +} +#else /* GEN_GEN < 7 */ static void blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size, @@ -261,18 +269,14 @@ blorp_emit_urb_config(struct blorp_batch *batch, assert(batch->blorp->driver_ctx == batch->driver_batch); struct brw_context *brw = batch->driver_batch; -#if GEN_GEN >= 7 - if (brw->urb.vsize >= vs_entry_size) - return; - - gen7_upload_urb(brw, vs_entry_size, false, false); -#elif GEN_GEN == 6 +#if GEN_GEN == 6 gen6_upload_urb(brw, vs_entry_size, false, 0); #else /* We calculate it now and emit later. */ brw_calculate_urb_fence(brw, 0, vs_entry_size, sf_entry_size); #endif } +#endif void genX(blorp_exec)(struct blorp_batch *batch, @@ -387,6 +391,12 @@ retry: brw->no_depth_or_stencil = !params->depth.enabled && !params->stencil.enabled; brw->ib.index_size = -1; + brw->urb.vsize = 0; + brw->urb.gs_present = false; + brw->urb.gsize = 0; + brw->urb.tess_present = false; + brw->urb.hsize = 0; + brw->urb.dsize = 0; if (params->dst.enabled) { brw_render_cache_add_bo(brw, params->dst.addr.buffer, |