diff options
| author | Jordan Justen <[email protected]> | 2013-07-09 15:19:55 -0700 |
|---|---|---|
| committer | Jordan Justen <[email protected]> | 2014-08-15 20:11:41 -0700 |
| commit | cfa19af966f52a153502f8296493b7b08960f7f5 (patch) | |
| tree | 1b2bebafc9916bfd3f794dcdda4fbd3d0aecc54d /src/mesa | |
| parent | 51b38106d74b1bd4fa2ce552f489c374bdffa812 (diff) | |
i965/gen6 depth surface: calculate LOD being rendered to
(08ef1dd for gen6)
This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Topi Pohjolainen <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_blorp.cpp | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_depth_state.c | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 0b1d0977ccd..96825c67787 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -783,6 +783,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t surftype; unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1); GLenum gl_target = params->depth.mt->target; + unsigned int lod; switch (gl_target) { case GL_TEXTURE_CUBE_MAP_ARRAY: @@ -806,6 +807,8 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, NULL, &tile_mask_x, &tile_mask_y); + lod = params->depth.level - params->depth.mt->first_level; + /* 3DSTATE_DEPTH_BUFFER */ { uint32_t tile_x = draw_x & tile_mask_x; diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c index 8ee969fc1b6..9e0357746b2 100644 --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c @@ -49,6 +49,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, uint32_t surftype; unsigned int depth = 1; GLenum gl_target = GL_TEXTURE_2D; + unsigned int lod; const struct intel_renderbuffer *irb = NULL; const struct gl_renderbuffer *rb = NULL; @@ -97,6 +98,8 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, break; } + lod = irb ? irb->mt_level - irb->mt->first_level : 0; + BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) | |