summaryrefslogtreecommitdiffstats
path: root/src/mesa
diff options
context:
space:
mode:
authorKenneth Graunke <[email protected]>2012-11-29 13:35:15 -0800
committerKenneth Graunke <[email protected]>2013-11-21 00:26:11 -0800
commit36c3faf4bf41d6618a3b0fcd565f4907a1633a40 (patch)
tree73eed9d5bb6763f9d7959eec273a56bae69a4f3e /src/mesa
parent01ae16a0e7d95f408016ff5b07bc647ad5608841 (diff)
i965: Disable BLORP on Broadwell for now.
BLORP is essential. However, porting it to Gen8 is a huge amount of work. Disabling it for now allows us to proceed with basic hardware enablement. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp_blit.cpp4
-rw-r--r--src/mesa/drivers/dri/i965/brw_clear.c4
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.cpp3
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c2
4 files changed, 8 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index d54b9263392..2d2edc1649c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -350,7 +350,7 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
struct intel_mipmap_tree *dst_mt = intel_image->mt;
/* BLORP is not supported before Gen6. */
- if (brw->gen < 6)
+ if (brw->gen < 6 || brw->gen >= 8)
return false;
if (_mesa_get_format_base_format(src_mt->format) !=
@@ -440,7 +440,7 @@ brw_blorp_framebuffer(struct brw_context *brw,
GLbitfield mask, GLenum filter)
{
/* BLORP is not supported before Gen6. */
- if (brw->gen < 6)
+ if (brw->gen < 6 || brw->gen >= 8)
return mask;
static GLbitfield buffer_bits[] = {
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index a727e6ec41c..d94e2597662 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -111,7 +111,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
struct intel_mipmap_tree *mt = depth_irb->mt;
struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
- if (brw->gen < 6)
+ if (brw->gen < 6 || brw->gen >= 8)
return false;
if (!intel_renderbuffer_has_hiz(depth_irb))
@@ -230,7 +230,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
}
/* BLORP is currently only supported on Gen6+. */
- if (brw->gen >= 6) {
+ if (brw->gen >= 6 && brw->gen < 8) {
if (mask & BUFFER_BITS_COLOR) {
if (brw_blorp_clear_color(brw, fb, partial_clear)) {
debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index d48153824de..3368d41136b 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -851,6 +851,9 @@ void
gen7_blorp_exec(struct brw_context *brw,
const brw_blorp_params *params)
{
+ if (brw->gen >= 8)
+ return;
+
brw_blorp_prog_data *prog_data = NULL;
uint32_t cc_blend_state_offset = 0;
uint32_t cc_state_offset = 0;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 292c3120b50..38898032532 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -202,7 +202,7 @@ intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
/* MCS support does not exist prior to Gen7 */
- if (brw->gen < 7)
+ if (brw->gen < 7 || brw->gen >= 8)
return false;
/* MCS is only supported for color buffers */