diff options
| author | Eric Anholt <[email protected]> | 2013-10-29 01:06:09 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2013-10-30 17:50:51 -0700 |
| commit | 32ac5634d6c830c93dad5349418ec8db85ec6bde (patch) | |
| tree | a4f88699f5020757c571f4fed3cb1f221833724d /src/mesa | |
| parent | bbb77fc2f19ed37f0ef9243b11bb4f74d9ca677c (diff) | |
i965/fs: Update an ancient, wrong comment about reg_offset.
This hasn't been true since SIMD16 mode was added.
Reviewed-by: Paul Berry <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index 5b783137ddf..5f331e17a58 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -88,9 +88,11 @@ public: */ int reg; /** - * For virtual registers, this is a hardware register offset from - * the start of the register block (for example, a constant index - * in an array access). + * Offset from the start of the contiguous register block. + * + * For pre-register-allocation GRFs, this is in units of a float per pixel + * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode). + * For uniforms, this is in units of 1 float. */ int reg_offset; /** Register type. BRW_REGISTER_TYPE_* */ |