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authorAndre Maasikas <[email protected]>2009-10-20 11:45:39 +0300
committerAndre Maasikas <[email protected]>2009-10-22 09:42:42 +0300
commitb86302283b48654682e0580c53ece01bf095fa95 (patch)
tree94b69a09e6195110a9c3964fc755ed1a67c4cf83 /src/mesa
parent5283a3fb25b2667501eb782fb461c981200a65ef (diff)
r600: add beginnings of ARL instruction
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.c35
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.h1
2 files changed, 33 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index a683008746d..d0eb9949a66 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -355,6 +355,7 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm)
return 2;
case SQ_OP2_INST_MOV:
+ case SQ_OP2_INST_MOVA_FLOOR:
case SQ_OP2_INST_FRACT:
case SQ_OP2_INST_FLOOR:
case SQ_OP2_INST_EXP_IEEE:
@@ -2064,7 +2065,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm)
}
//other bits
- alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_LOOP;
+ alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_AR_X;
if( (is_single_scalar_operation == GL_TRUE)
|| (GL_TRUE == bSplitInst) )
@@ -2398,6 +2399,35 @@ GLboolean assemble_ADD(r700_AssemblerBase *pAsm)
return GL_TRUE;
}
+GLboolean assemble_ARL(r700_AssemblerBase *pAsm)
+{ /* TODO: ar values dont' persist between clauses */
+ if( GL_FALSE == checkop1(pAsm) )
+ {
+ return GL_FALSE;
+ }
+
+ pAsm->D.dst.opcode = SQ_OP2_INST_MOVA_FLOOR;
+ setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
+ pAsm->D.dst.rtype = DST_REG_TEMPORARY;
+ pAsm->D.dst.reg = 0;
+ pAsm->D.dst.writex = 0;
+ pAsm->D.dst.writey = 0;
+ pAsm->D.dst.writez = 0;
+ pAsm->D.dst.writew = 0;
+
+ if( GL_FALSE == assemble_src(pAsm, 0, -1) )
+ {
+ return GL_FALSE;
+ }
+
+ if( GL_FALSE == next_ins(pAsm) )
+ {
+ return GL_FALSE;
+ }
+
+ return GL_TRUE;
+}
+
GLboolean assemble_BAD(char *opcode_str)
{
radeon_error("Not yet implemented instruction (%s)\n", opcode_str);
@@ -3812,8 +3842,7 @@ GLboolean AssembleInstr(GLuint uiNumberInsts,
break;
case OPCODE_ARL:
- radeon_error("Not yet implemented instruction OPCODE_ARL \n");
- //if ( GL_FALSE == assemble_BAD("ARL") )
+ if ( GL_FALSE == assemble_ARL(pR700AsmCode) )
return GL_FALSE;
break;
case OPCODE_ARR:
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h
index 73bb8bac55d..d639592702a 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.h
+++ b/src/mesa/drivers/dri/r600/r700_assembler.h
@@ -461,6 +461,7 @@ GLboolean next_ins(r700_AssemblerBase *pAsm);
GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode);
GLboolean assemble_ABS(r700_AssemblerBase *pAsm);
GLboolean assemble_ADD(r700_AssemblerBase *pAsm);
+GLboolean assemble_ARL(r700_AssemblerBase *pAsm);
GLboolean assemble_BAD(char *opcode_str);
GLboolean assemble_CMP(r700_AssemblerBase *pAsm);
GLboolean assemble_COS(r700_AssemblerBase *pAsm);