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authorFrancisco Jerez <[email protected]>2015-08-04 19:07:19 +0300
committerFrancisco Jerez <[email protected]>2015-08-06 14:12:12 +0300
commitee977183dcb543c919d0d70dde610cb191d5a3ea (patch)
treeb11629613fb5d7e66b981dc8cc40330debe8fad8 /src/mesa/vbo/vbo.h
parent42a18ca76057621ae7d8812b29ea2245d6ff282d (diff)
i965/fs: Lower arithmetic instructions with register regions of unsupported width.
This extends the SIMD lowering pass to enforce the hardware limitation that no directly-addressed source may read more than 2 physical GRFs. One can easily go over this limit when doing 64-bit arithmetic (e.g. FP64 or extended-precision integer MULs) or SIMD32, so it's nice to be able to just emit an instruction of the intended execution size from the visitor and let the lowering pass deal with this restriction transparently. Some hardware arithmetic instructions are not handled here, including all instructions that use the accumulator implicitly (which the SIMD lowering pass deliberately doesn't handle), instructions with non-per-channel sources (e.g. LINE or PLANE) and SEND-like instructions, which need special handling most likely as virtual opcodes. Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa/vbo/vbo.h')
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