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authorAntia Puentes <[email protected]>2015-09-22 18:17:45 +0200
committerAntia Puentes <[email protected]>2015-09-23 13:12:25 +0200
commitf2e75ac88a92ab2180de576aca298929cfce03f2 (patch)
tree073295cf1e47911daeabc9ee80b65342d18d0d78 /src/mesa/tnl_dd
parentcf439951b791827677e96d29e209b5fc08d07a2e (diff)
i965/vec4: Don't coalesce regs in Gen6 MATH ops if reswizzle/writemask needed
Gen6 MATH instructions can not execute in align16 mode, so swizzles or writemasking are not allowed. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92033 Reviewed-by: Matt Turner <[email protected]>
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