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author | Francisco Jerez <[email protected]> | 2015-08-04 19:04:55 +0300 |
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committer | Francisco Jerez <[email protected]> | 2015-08-06 14:12:12 +0300 |
commit | 8f5d0988ea2ccaba7f049f113b652f331524d2a6 (patch) | |
tree | c86698766eec7f268fc40a8eff912c966783f0b0 /src/mesa/swrast_setup | |
parent | f7ac4ef4eeea737115d0b574fed7ecae46426072 (diff) |
i965: Define virtual instruction to calculate the high 32 bits of a multiply.
This instruction will translate to the MUL/MACH sequence that computes
the high 32-bits of the result of a 64-bit multiply. Before Gen8
integer operations that used the accumulator were limited to 8-wide,
but the SIMD lowering pass can easily be hooked up to sidestep this
limitation, we just need a virtual opcode to represent the MUL/MACH
sequence in the IR.
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/mesa/swrast_setup')
0 files changed, 0 insertions, 0 deletions