diff options
| author | Anuj Phogat <[email protected]> | 2018-05-31 16:03:44 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-07-09 15:38:42 -0700 |
| commit | 2badf0e85b3a54119b08c559dc18aed43a156295 (patch) | |
| tree | 9226ec23b0f30aa7c067431678ee3ad914a4f881 /src/mesa/swrast_setup/ss_vb.h | |
| parent | c1d8300117891ec87762caa30d14307622c65bcf (diff) | |
i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS
CACHE_MODE_SS is not listed in gfxspecs table for user mode
non-privileged registers. So, making any changes from Mesa
will do nothing. Kernel is already setting this bit in
CACHE_MODE_SS register which is saved/restored to/from
the HW context image.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/mesa/swrast_setup/ss_vb.h')
0 files changed, 0 insertions, 0 deletions