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authorAbdiel Janulgue <[email protected]>2015-04-15 13:04:45 +0300
committerAbdiel Janulgue <[email protected]>2015-07-18 16:16:54 +0300
commit190756482e62cb57e2bc8c798181e5f0171726fb (patch)
treed7c8cb2ea1e5740f4c527da792c94cb141a0b290 /src/mesa/swrast/s_texture.c
parent090529af1828817344e0850ef27eebd1f096eb5f (diff)
i965: Enable hardware-generated binding tables on render path.
This patch implements the binding table enable command which is also used to allocate a binding table pool where where hardware-generated binding table entries are flushed into. Each binding table offset in the binding table pool is unique per each shader stage that are enabled within a batch. Also insert the required brw_tracked_state objects to enable hw-generated binding tables in normal render path. v2: - Use MOCS in binding table pool alloc for GEN8 - Fix spurious offset when allocating binding table pool entry and start from zero instead. v3: - Include GEN8 fix for spurious offset above. v4: - Fixup wrong packet length in enable/disable hw-binding table for GEN8 (Ville). - Don't invoke HW-binding table disable command when we dont have resource streamer (Chris). v5: - Reorder the state cache invalidate flush so it happens in-between enabling hw-generated binding tables and the previous sw-binding table GPU state (Chris). v6: - Do the same fix in v5 for gen7_disable_hw_binding_tables(). - Adhere to coding guidelines and make comments more informative. Cc: [email protected] Cc: [email protected] Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
Diffstat (limited to 'src/mesa/swrast/s_texture.c')
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