diff options
| author | Ian Romanick <[email protected]> | 2005-11-08 22:40:26 +0000 |
|---|---|---|
| committer | Ian Romanick <[email protected]> | 2005-11-08 22:40:26 +0000 |
| commit | 4884db6eb29d30a16e5bf72da08ea6095ecd3339 (patch) | |
| tree | b4087a2a68b008ff318a55d643d9ea0970e51ed0 /src/mesa/shader/program.c | |
| parent | e1a5edf083efb065f97ec08592ae2c4ff6fc6662 (diff) | |
This patch adds the missing NV_vertex_program2 and NV_vertex_program3
instructions to the various internal tables. It does not add support for
them to the parser nor does it add support for them to the program
interpreter.
It also corrects some errors in the comments in program_instruction.h.
This patch breaks the instruction union in t_vb_arbprogram.h. The opcode
field in that union was only 6 bits. When there were only 59+3 instructions
that worked fine. However, this patch increases the base instruction count
to 69. This requires 7 bits. The problem is that increasing the opcode
width to 7 bits increases the size of instruction::rsw to 33 bits. I've
increased the size of the union to 64-bit, but this is just a temporary hack
(and probably breaks the build on some systems).
Diffstat (limited to 'src/mesa/shader/program.c')
| -rw-r--r-- | src/mesa/shader/program.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mesa/shader/program.c b/src/mesa/shader/program.c index a77c447e284..d46fadefcab 100644 --- a/src/mesa/shader/program.c +++ b/src/mesa/shader/program.c @@ -978,7 +978,12 @@ struct instruction_info static const struct instruction_info InstInfo[MAX_OPCODE] = { { OPCODE_ABS, "ABS", 1 }, { OPCODE_ADD, "ADD", 2 }, + { OPCODE_ARA, "ARA", 1 }, { OPCODE_ARL, "ARL", 1 }, + { OPCODE_ARL_NV, "ARL", 1 }, + { OPCODE_ARR, "ARL", 1 }, + { OPCODE_BRA, "BRA", 1 }, + { OPCODE_CAL, "CAL", 1 }, { OPCODE_CMP, "CMP", 3 }, { OPCODE_COS, "COS", 1 }, { OPCODE_DDX, "DDX", 1 }, @@ -1008,9 +1013,12 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = { { OPCODE_PK4B, "PK4B", 1 }, { OPCODE_PK4UB, "PK4UB", 1 }, { OPCODE_POW, "POW", 2 }, + { OPCODE_POPA, "POPA", 0 }, { OPCODE_PRINT, "PRINT", 1 }, + { OPCODE_PUSHA, "PUSHA", 0 }, { OPCODE_RCC, "RCC", 1 }, { OPCODE_RCP, "RCP", 1 }, + { OPCODE_RET, "RET", 1 }, { OPCODE_RFL, "RFL", 1 }, { OPCODE_RSQ, "RSQ", 1 }, { OPCODE_SCS, "SCS", 1 }, @@ -1022,12 +1030,14 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = { { OPCODE_SLE, "SLE", 2 }, { OPCODE_SLT, "SLT", 2 }, { OPCODE_SNE, "SNE", 2 }, + { OPCODE_SSG, "SSG", 1 }, { OPCODE_STR, "STR", 0 }, { OPCODE_SUB, "SUB", 2 }, { OPCODE_SWZ, "SWZ", 1 }, { OPCODE_TEX, "TEX", 1 }, { OPCODE_TXB, "TXB", 1 }, { OPCODE_TXD, "TXD", 3 }, + { OPCODE_TXL, "TXL", 1 }, { OPCODE_TXP, "TXP", 1 }, { OPCODE_TXP_NV, "TXP", 1 }, { OPCODE_UP2H, "UP2H", 1 }, |