diff options
| author | Olivier Galibert <[email protected]> | 2012-05-08 20:40:36 +0200 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2012-06-07 00:06:18 -0700 |
| commit | e16b0a51be7866f3856b62b295df2bcf49e02384 (patch) | |
| tree | 6b5563014c5781ae0f3b0e8c0fdf8e1110768598 /src/mesa/program | |
| parent | abe976755318fa9dd88a5c48289623ab7c12ce02 (diff) | |
glsl: Bitwise conversion operator support in the software renderers.
TGSI doesn't need an opcode, since registers are untyped (but beware
once doubles come into the scene). Mesa IR doesn't handle native
integers, so trying to handle them there is worthless, the case
entries are only added for warning reasons.
It was only tested with softpipe, since llvmpipe doesn't support glsl
1.3 yet.
Signed-off-by: Olivier Galibert <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/program')
| -rw-r--r-- | src/mesa/program/ir_to_mesa.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp index c021c6956e6..22454000509 100644 --- a/src/mesa/program/ir_to_mesa.cpp +++ b/src/mesa/program/ir_to_mesa.cpp @@ -1407,6 +1407,11 @@ ir_to_mesa_visitor::visit(ir_expression *ir) emit(ir, OPCODE_SNE, result_dst, op[0], src_reg_for_float(0.0)); break; + case ir_unop_bitcast_f2i: // Ignore these 4, they can't happen here anyway + case ir_unop_bitcast_f2u: + case ir_unop_bitcast_i2f: + case ir_unop_bitcast_u2f: + break; case ir_unop_trunc: emit(ir, OPCODE_TRUNC, result_dst, op[0]); break; |