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authorMatt Turner <[email protected]>2016-02-27 11:06:25 -0800
committerMatt Turner <[email protected]>2016-03-01 11:41:29 -0800
commit7b50b0457db3acffcc2a7de092df346fa314aa95 (patch)
tree5ed9937b2b888336d52a7808166e03cde938096b /src/mesa/program/ir_to_mesa.cpp
parent9e11ff7e11c87dd19d2274644bca7a869ff2143d (diff)
program: Remove condition-code and precision support.
Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Acked-by: Brian Paul <[email protected]>
Diffstat (limited to 'src/mesa/program/ir_to_mesa.cpp')
-rw-r--r--src/mesa/program/ir_to_mesa.cpp7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index c7ca3dc6cd6..a208c05a067 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -105,7 +105,6 @@ public:
this->file = file;
this->index = 0;
this->writemask = writemask;
- this->cond_mask = COND_TR;
this->reladdr = NULL;
}
@@ -114,7 +113,6 @@ public:
this->file = PROGRAM_UNDEFINED;
this->index = 0;
this->writemask = 0;
- this->cond_mask = COND_TR;
this->reladdr = NULL;
}
@@ -123,7 +121,6 @@ public:
gl_register_file file; /**< PROGRAM_* from Mesa */
int index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
- GLuint cond_mask:4;
/** Register index should be offset by the integer in this reg. */
src_reg *reladdr;
};
@@ -144,7 +141,6 @@ dst_reg::dst_reg(src_reg reg)
this->file = reg.file;
this->index = reg.index;
this->writemask = WRITEMASK_XYZW;
- this->cond_mask = COND_TR;
this->reladdr = reg.reladdr;
}
@@ -159,7 +155,6 @@ public:
src_reg src[3];
/** Pointer to the ir source this tree came from for debugging */
ir_instruction *ir;
- GLboolean cond_update;
bool saturate;
int sampler; /**< sampler index */
int tex_target; /**< One of TEXTURE_*_INDEX */
@@ -2769,12 +2764,10 @@ get_mesa_program(struct gl_context *ctx,
i = 0;
foreach_in_list(const ir_to_mesa_instruction, inst, &v.instructions) {
mesa_inst->Opcode = inst->op;
- mesa_inst->CondUpdate = inst->cond_update;
if (inst->saturate)
mesa_inst->Saturate = GL_TRUE;
mesa_inst->DstReg.File = inst->dst.file;
mesa_inst->DstReg.Index = inst->dst.index;
- mesa_inst->DstReg.CondMask = inst->dst.cond_mask;
mesa_inst->DstReg.WriteMask = inst->dst.writemask;
mesa_inst->DstReg.RelAddr = inst->dst.reladdr != NULL;
mesa_inst->SrcReg[0] = mesa_src_reg_from_ir_src_reg(inst->src[0]);