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authorBrian <[email protected]>2007-10-23 15:08:54 -0600
committerBrian <[email protected]>2007-10-23 15:08:54 -0600
commit4664261f8d8fefa347bf38a224f6584d0fdeebfc (patch)
treef2bfecda388f5ae02875aed15a09fdaf4f3852a9 /src/mesa/pipe
parent3df65af849280863a15fefcb11f8304b83c9ffa0 (diff)
Fix vertex cache bug that allows multiple vertices to fall into the same slot.
Need to set the slot's bit in draw->vcache.referenced even when there was a cache hit since flushing the primitive buffer will have cleared the bitfield but not the cache's vertex indexes. Fixes a bug found when drawing long triangle fans but could be hit by other prim types as well. An alternate fix would be to call draw_vertex_cache_invalidate() from draw_vertex_cache_unreference().
Diffstat (limited to 'src/mesa/pipe')
-rw-r--r--src/mesa/pipe/draw/draw_vertex_cache.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/pipe/draw/draw_vertex_cache.c b/src/mesa/pipe/draw/draw_vertex_cache.c
index dc939d6d14f..56a4c34df50 100644
--- a/src/mesa/pipe/draw/draw_vertex_cache.c
+++ b/src/mesa/pipe/draw/draw_vertex_cache.c
@@ -59,6 +59,8 @@ static struct vertex_header *get_vertex( struct draw_context *draw,
{
unsigned slot = (i + (i>>5)) % VCACHE_SIZE;
+ assert(slot < 32); /* so we don't exceed the bitfield size below */
+
/* Cache miss?
*/
if (draw->vcache.idx[slot] != i) {
@@ -80,6 +82,7 @@ static struct vertex_header *get_vertex( struct draw_context *draw,
/* Add to vertex shader queue:
*/
+ assert(draw->vs.queue_nr < VS_QUEUE_LENGTH);
draw->vs.queue[draw->vs.queue_nr].dest = draw->vcache.vertex[slot];
draw->vs.queue[draw->vs.queue_nr].elt = i;
draw->vs.queue_nr++;
@@ -94,8 +97,14 @@ static struct vertex_header *get_vertex( struct draw_context *draw,
}
else {
// fprintf(stderr, "*");
+ /* primitive flushing may have cleared the bitfield but did not
+ * clear the idx[] array values. Set the bit now. This fixes a
+ * bug found when drawing long triangle fans.
+ */
+ draw->vcache.referenced |= (1 << slot);
}
+
return draw->vcache.vertex[slot];
}