gallium: clean-up, simplification of mipmapped textures

Remove pipe_texture->first_level (always implicitly zero).  This means there's
never any unused mipmap levels at the top.
In the state tracker, we no longer re-layout mipmapped textures if the
MinLod/MaxLod texture parameters change.  It's up to the driver to obey the
pipe_sampler->min/max_lod clamps.

2 files changed, 5 insertions, 5 deletions

diff --git a/src/mesa/pipe/i965simple/brw_tex_layout.c b/src/mesa/pipe/i965simple/brw_tex_layout.c
index 405fd1f7949..90561f1307d 100644
--- a/src/mesa/pipe/i965simple/brw_tex_layout.c
+++ b/src/mesa/pipe/i965simple/brw_tex_layout.c
@@ -146,7 +146,7 @@ static void i945_miptree_layout_2d(struct brw_texture *tex)
     * constraints of mipmap placement push the right edge of the
     * 2nd mipmap out past the width of its parent.
     */
-   if (pt->first_level != pt->last_level) {
+   if (pt->last_level > 0) {
       unsigned mip1_width;
 
       if (pt->compressed) {
@@ -168,7 +168,7 @@ static void i945_miptree_layout_2d(struct brw_texture *tex)
    tex->pitch = align(tex->pitch * pt->cpp, 4) / pt->cpp;
    tex->total_height = 0;
 
-   for ( level = pt->first_level ; level <= pt->last_level ; level++ ) {
+   for (level = 0; level <= pt->last_level; level++) {
       unsigned img_height;
 
       intel_miptree_set_level_info(tex, level, 1, x, y, width,
@@ -187,7 +187,7 @@ static void i945_miptree_layout_2d(struct brw_texture *tex)
 
       /* Layout_below: step right after second mipmap.
        */
-      if (level == pt->first_level + 1) {
+      if (level == 1) {
 	 x += align(width, align_w);
       }
       else {
@@ -234,7 +234,7 @@ static boolean brw_miptree_layout(struct pipe_context *pipe, struct brw_texture
       pack_x_pitch = tex->pitch;
       pack_x_nr = 1;
 
-      for ( level = pt->first_level ; level <= pt->last_level ; level++ ) {
+      for (level = 0; level <= pt->last_level; level++) {
 	 unsigned nr_images = pt->target == PIPE_TEXTURE_3D ? depth : 6;
 	 int x = 0;
 	 int y = 0;
diff --git a/src/mesa/pipe/i965simple/brw_wm_surface_state.c b/src/mesa/pipe/i965simple/brw_wm_surface_state.c
index cbb4f2efd3b..d16d919bce9 100644
--- a/src/mesa/pipe/i965simple/brw_wm_surface_state.c
+++ b/src/mesa/pipe/i965simple/brw_wm_surface_state.c
@@ -154,7 +154,7 @@ void brw_update_texture_surface( struct brw_context *brw,
    /* Updated in emit_reloc */
    surf.ss1.base_addr = brw_buffer_offset( brw, tObj->buffer );
 
-   surf.ss2.mip_count = tObj->base.last_level - tObj->base.first_level;
+   surf.ss2.mip_count = tObj->base.last_level;
    surf.ss2.width = tObj->base.width[0] - 1;
    surf.ss2.height = tObj->base.height[0] - 1;