mesa: Make gl_program::InputsRead 64 bits.

Make gl_program::InputsRead a 64 bits bitfield.
Adapt the intel and radeon driver to handle a 64 bits
InputsRead value.

Signed-off-by: Mathias Froehlich <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>

9 files changed, 40 insertions, 24 deletions

diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 063e155d289..4f016a3f69d 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1148,7 +1148,7 @@ fixup_depth_write(struct i915_fragment_program *p)
 static void
 check_wpos(struct i915_fragment_program *p)
 {
-   GLuint inputs = p->FragProg.Base.InputsRead;
+   GLbitfield64 inputs = p->FragProg.Base.InputsRead;
    GLint i;
 
    p->wpos_tex = -1;
@@ -1337,7 +1337,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
    struct i915_fragment_program *p =
       (struct i915_fragment_program *) ctx->FragmentProgram._Current;
 
-   const GLuint inputsRead = p->FragProg.Base.InputsRead;
+   const GLbitfield64 inputsRead = p->FragProg.Base.InputsRead;
    GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
    GLuint s2 = S2_TEXCOORD_NONE;
    int i, offset = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index c1b123f5bd5..87675e98373 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -379,7 +379,7 @@ struct brw_vs_prog_data {
    GLuint nr_pull_params; /**< number of dwords referenced by pull_param[] */
    GLuint total_scratch;
 
-   GLuint inputs_read;
+   GLbitfield64 inputs_read;
 
    /* Used for calculating urb partitions:
     */
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index bd3d9691439..331f2a0915e 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -355,7 +355,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
    struct gl_context *ctx = &brw->intel.ctx;
    struct intel_context *intel = intel_context(ctx);
    /* CACHE_NEW_VS_PROG */
-   GLbitfield vs_inputs = brw->vs.prog_data->inputs_read;
+   GLbitfield64 vs_inputs = brw->vs.prog_data->inputs_read;
    const unsigned char *ptr = NULL;
    GLuint interleaved = 0, total_size = 0;
    unsigned int min_index = brw->vb.min_index;
@@ -373,10 +373,10 @@ static void brw_prepare_vertices(struct brw_context *brw)
    /* Accumulate the list of enabled arrays. */
    brw->vb.nr_enabled = 0;
    while (vs_inputs) {
-      GLuint i = ffs(vs_inputs) - 1;
+      GLuint i = ffsll(vs_inputs) - 1;
       struct brw_vertex_element *input = &brw->vb.inputs[i];
 
-      vs_inputs &= ~(1 << i);
+      vs_inputs &= ~BITFIELD64_BIT(i);
       if (input->glarray->Size && get_size(input->glarray->Type))
          brw->vb.enabled[brw->vb.nr_enabled++] = input;
    }
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index 967f82e1916..81d5f884a5a 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -207,7 +207,7 @@ do_vs_prog(struct brw_context *brw,
 
    if (c.key.copy_edgeflag) {
       c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_EDGE);
-      c.prog_data.inputs_read |= 1<<VERT_ATTRIB_EDGEFLAG;
+      c.prog_data.inputs_read |= VERT_BIT_EDGEFLAG;
    }
 
    /* Put dummy slots into the VUE for the SF to put the replaced
@@ -318,7 +318,7 @@ static void brw_upload_vs_prog(struct brw_context *brw)
 
    /* BRW_NEW_VERTICES */
    for (i = 0; i < VERT_ATTRIB_MAX; i++) {
-      if (vp->program.Base.InputsRead & (1 << i) &&
+      if (vp->program.Base.InputsRead & BITFIELD64_BIT(i) &&
 	  brw->vb.inputs[i].glarray->Type == GL_FIXED) {
 	 key.gl_fixed_input_size[i] = brw->vb.inputs[i].glarray->Size;
       }
diff --git a/src/mesa/drivers/dri/i965/brw_vs_constval.c b/src/mesa/drivers/dri/i965/brw_vs_constval.c
index 8b7993a7dec..9ce5ab379ea 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_constval.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_constval.c
@@ -202,7 +202,7 @@ static void calc_wm_input_sizes( struct brw_context *brw )
       t.twoside = 1;
 
    for (i = 0; i < VERT_ATTRIB_MAX; i++) 
-      if (vp->program.Base.InputsRead & (1<<i))
+      if (vp->program.Base.InputsRead & BITFIELD64_BIT(i))
 	 set_active_component(&t, PROGRAM_INPUT, i, 
 			      szflag[get_input_size(brw, i)]);
       
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index e39b3dd0a95..bcaef04bcf3 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -311,7 +311,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
     */
    c->nr_inputs = 0;
    for (i = 0; i < VERT_ATTRIB_MAX; i++) {
-      if (c->prog_data.inputs_read & (1 << i)) {
+      if (c->prog_data.inputs_read & BITFIELD64_BIT(i)) {
 	 c->nr_inputs++;
 	 c->regs[PROGRAM_INPUT][i] = brw_vec8_grf(reg, 0);
 	 reg++;
@@ -1820,7 +1820,7 @@ brw_vs_rescale_gl_fixed(struct brw_vs_compile *c)
    int i;
 
    for (i = 0; i < VERT_ATTRIB_MAX; i++) {
-      if (!(c->prog_data.inputs_read & (1 << i)))
+      if (!(c->prog_data.inputs_read & BITFIELD64_BIT(i)))
 	 continue;
 
       if (c->key.gl_fixed_input_size[i] != 0) {
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 070220a5077..10775840755 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -184,7 +184,7 @@ upload_wm_state(struct brw_context *brw)
       dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
 
    /* BRW_NEW_FRAGMENT_PROGRAM */
-   if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
+   if (fp->program.Base.InputsRead & FRAG_BIT_WPOS)
       dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
       dw5 |= GEN6_WM_COMPUTED_DEPTH;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index f38d2f1155f..a99483668f6 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -58,7 +58,7 @@ upload_wm_state(struct brw_context *brw)
       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 
    /* BRW_NEW_FRAGMENT_PROGRAM */
-   if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
+   if (fp->program.Base.InputsRead & FRAG_BIT_WPOS)
       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
       writes_depth = true;
diff --git a/src/mesa/drivers/dri/r200/r200_vertprog.c b/src/mesa/drivers/dri/r200/r200_vertprog.c
index 697073e2510..d26affb1fda 100644
--- a/src/mesa/drivers/dri/r200/r200_vertprog.c
+++ b/src/mesa/drivers/dri/r200/r200_vertprog.c
@@ -535,20 +535,29 @@ static GLboolean r200_translate_vertex_program(struct gl_context *ctx, struct r2
       vp->inputmap_rev[3] = VERT_ATTRIB_FOG;
       array_count++;
    }
-   for (i = VERT_ATTRIB_TEX0; i <= VERT_ATTRIB_TEX5; i++) {
-      if (mesa_vp->Base.InputsRead & (1 << i)) {
-	 vp->inputs[i] = i - VERT_ATTRIB_TEX0 + 6;
-	 vp->inputmap_rev[8 + i - VERT_ATTRIB_TEX0] = i;
-	 free_inputs &= ~(1 << (i - VERT_ATTRIB_TEX0 + 6));
+   /* VERT_ATTRIB_TEX0-5 */
+   for (i = 0; i <= 5; i++) {
+      if (mesa_vp->Base.InputsRead & VERT_BIT_TEX(i)) {
+	 vp->inputs[VERT_ATTRIB_TEX(i)] = i + 6;
+	 vp->inputmap_rev[8 + i] = VERT_ATTRIB_TEX(i);
+	 free_inputs &= ~(1 << (i + 6));
 	 array_count++;
       }
    }
    /* using VERT_ATTRIB_TEX6/7 would be illegal */
+   for (; i < VERT_ATTRIB_TEX_MAX; i++) {
+      if (mesa_vp->Base.InputsRead & VERT_BIT_TEX(i)) {
+          if (R200_DEBUG & RADEON_FALLBACKS) {
+              fprintf(stderr, "texture attribute %d in vert prog\n", i);
+          }
+          return GL_FALSE;
+      }
+   }
    /* completely ignore aliasing? */
-   for (i = VERT_ATTRIB_GENERIC0; i < VERT_ATTRIB_MAX; i++) {
+   for (i = 0; i < VERT_ATTRIB_GENERIC_MAX; i++) {
       int j;
    /* completely ignore aliasing? */
-      if (mesa_vp->Base.InputsRead & (1 << i)) {
+      if (mesa_vp->Base.InputsRead & VERT_BIT_GENERIC(i)) {
 	 array_count++;
 	 if (array_count > 12) {
 	    if (R200_DEBUG & RADEON_FALLBACKS) {
@@ -560,10 +569,17 @@ static GLboolean r200_translate_vertex_program(struct gl_context *ctx, struct r2
 	    /* will always find one due to limited array_count */
 	    if (free_inputs & (1 << j)) {
 	       free_inputs &= ~(1 << j);
-	       vp->inputs[i] = j;
-	       if (j == 0) vp->inputmap_rev[j] = i; /* mapped to pos */
-	       else if (j < 12) vp->inputmap_rev[j + 2] = i; /* mapped to col/tex */
-	       else vp->inputmap_rev[j + 1] = i; /* mapped to pos1 */
+	       vp->inputs[VERT_ATTRIB_GENERIC(i)] = j;
+	       if (j == 0) {
+                  /* mapped to pos */
+                  vp->inputmap_rev[j] = VERT_ATTRIB_GENERIC(i);
+	       } else if (j < 12) {
+                  /* mapped to col/tex */
+                  vp->inputmap_rev[j + 2] = VERT_ATTRIB_GENERIC(i);
+	       } else {
+                  /* mapped to pos1 */
+                  vp->inputmap_rev[j + 1] = VERT_ATTRIB_GENERIC(i);
+               }
 	       break;
 	    }
 	 }