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authorJordan Justen <[email protected]>2014-06-29 12:06:33 -0700
committerJordan Justen <[email protected]>2015-03-09 23:56:51 -0700
commit26eabd189d9dd1e1e1c711ee4bcc8ff73c076d11 (patch)
tree7eaeaa4c24926a601305494cf3e304ab7487fe3f /src/mesa/drivers
parentaedcd466bb9d899e892f9d47f96fbca5e5647133 (diff)
i965/gen7: Don't rely directly on the hiz miptree structure
We are still allocating a miptree for hiz, but we only use fields from intel_miptree_aux_buffer. This will allow us to switch over to not allocating a miptree. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.cpp6
-rw-r--r--src/mesa/drivers/dri/i965/gen7_misc_state.c7
2 files changed, 7 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 6ba65d67f6c..fb6a0dd52aa 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -695,13 +695,13 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
/* 3DSTATE_HIER_DEPTH_BUFFER */
{
- struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_buf->mt;
+ struct intel_miptree_aux_buffer *hiz_buf = params->depth.mt->hiz_buf;
BEGIN_BATCH(3);
OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH((mocs << 25) |
- (hiz_mt->pitch - 1));
- OUT_RELOC(hiz_mt->bo,
+ (hiz_buf->pitch - 1));
+ OUT_RELOC(hiz_buf->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index cc74570ee37..f4f665219d6 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -145,12 +145,13 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
- struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
+ struct intel_miptree_aux_buffer *hiz_buf = depth_mt->hiz_buf;
+
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH((mocs << 25) |
- (hiz_mt->pitch - 1));
- OUT_RELOC(hiz_mt->bo,
+ (hiz_buf->pitch - 1));
+ OUT_RELOC(hiz_buf->bo,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER,
0);