diff options
| author | Kenneth Graunke <[email protected]> | 2017-07-31 22:04:25 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2017-08-02 10:01:34 -0700 |
| commit | 595a47b8293b1d97a3ae7dbfa8db703bfb4e7aae (patch) | |
| tree | 1bfa24c486478512fe7bf3aa491818d81c163f40 /src/mesa/drivers | |
| parent | 7cd50b9e47a8ad131795da270039da87e0175143 (diff) | |
i965: Delete pitch alignment assertion in get_blit_intratile_offset_el.
The cacheline alignment restriction is on the base address; the pitch
can be anything.
Fixes assertion failures when using primus (say, on glxgears, which
creates a 300x300 linear BGRX surface with a pitch of 1200):
intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch % 64 == 0' failed.
Cc: [email protected]
Reviewed-by: Chris Wilson <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_blit.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index eca87368047..b1db7aa2293 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -187,7 +187,6 @@ get_blit_intratile_offset_el(const struct brw_context *brw, * The offsets we get from ISL in the tiled case are already aligned. * In the linear case, we need to do some of our own aligning. */ - assert(mt->surf.row_pitch % 64 == 0); uint32_t delta = *base_address_offset & 63; assert(delta % mt->cpp == 0); *base_address_offset -= delta; |